@@ -103,6 +103,11 @@ MCCodeEmitter *llvm::createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
103103 return new AMDGPUMCCodeEmitter (MCII, *Ctx.getRegisterInfo ());
104104}
105105
106+ static void addFixup (SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
107+ const MCExpr *Value, uint16_t Kind, bool PCRel = false ) {
108+ Fixups.push_back (MCFixup::create (Offset, Value, Kind, PCRel));
109+ }
110+
106111// Returns the encoding value to use if the given integer is an integer inline
107112// immediate value, or 0 if it is not.
108113template <typename IntTy>
@@ -445,8 +450,7 @@ void AMDGPUMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
445450
446451 if (MO.isExpr ()) {
447452 const MCExpr *Expr = MO.getExpr ();
448- MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
449- Fixups.push_back (MCFixup::create (0 , Expr, Kind));
453+ addFixup (Fixups, 0 , Expr, AMDGPU::fixup_si_sopp_br, true );
450454 Op = APInt::getZero (96 );
451455 } else {
452456 getMachineOpValue (MI, MO, Op, Fixups, STI);
@@ -661,8 +665,7 @@ void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
661665 const MCInstrDesc &Desc = MCII.get (MI.getOpcode ());
662666 uint32_t Offset = Desc.getSize ();
663667 assert (Offset == 4 || Offset == 8 );
664-
665- Fixups.push_back (MCFixup::create (Offset, MO.getExpr (), Kind));
668+ addFixup (Fixups, Offset, MO.getExpr (), Kind, Kind == FK_PCRel_4);
666669 }
667670
668671 const MCInstrDesc &Desc = MCII.get (MI.getOpcode ());
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