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init support
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8 files changed

+796
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lines changed

8 files changed

+796
-4
lines changed

‎llvm/lib/Target/RISCV/RISCVCallingConv.cpp‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -545,7 +545,12 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
545545
unsigned StoreSizeBytes = XLen / 8;
546546
Align StackAlign = Align(XLen / 8);
547547

548-
if (ValVT.isVector() || ValVT.isRISCVVectorTuple()) {
548+
// Check if this is a P extension vector type that should use GPRs
549+
bool isPExtVec = Subtarget.hasStdExtP() && ValVT.isVector() &&
550+
((Subtarget.is64Bit() && (ValVT == MVT::v4i16 || ValVT == MVT::v8i8 || ValVT == MVT::v2i32)) ||
551+
(!Subtarget.is64Bit() && (ValVT == MVT::v2i16 || ValVT == MVT::v4i8)));
552+
553+
if ((ValVT.isVector() || ValVT.isRISCVVectorTuple()) && !isPExtVec) {
549554
Reg = allocateRVVReg(ValVT, ValNo, State, TLI);
550555
if (Reg) {
551556
// Fixed-length vectors are located in the corresponding scalable-vector
@@ -604,8 +609,9 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
604609

605610
assert(((ValVT.isFloatingPoint() && !ValVT.isVector()) || LocVT == XLenVT ||
606611
(TLI.getSubtarget().hasVInstructions() &&
607-
(ValVT.isVector() || ValVT.isRISCVVectorTuple()))) &&
608-
"Expected an XLenVT or vector types at this stage");
612+
(ValVT.isVector() || ValVT.isRISCVVectorTuple())) ||
613+
isPExtVec) &&
614+
"Expected an XLenVT, P extension vector, or RVV vector types at this stage");
609615

610616
if (Reg) {
611617
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2566,6 +2566,23 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
25662566
CurDAG->RemoveDeadNode(Node);
25672567
return;
25682568
}
2569+
// Special case: drop bitcasts between scalar and P extension fixed vector types
2570+
// since both use the same GPR register class
2571+
if (Subtarget->hasStdExtP()) {
2572+
bool shouldEliminate =
2573+
(Subtarget->is64Bit() &&
2574+
(((VT == MVT::i64) && (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8)) ||
2575+
((SrcVT == MVT::i64) && (VT == MVT::v2i32 || VT == MVT::v4i16 || VT == MVT::v8i8)))) ||
2576+
(!Subtarget->is64Bit() &&
2577+
(((VT == MVT::i32) && (SrcVT == MVT::v2i16 || SrcVT == MVT::v4i8)) ||
2578+
((SrcVT == MVT::i32) && (VT == MVT::v2i16 || VT == MVT::v4i8))));
2579+
2580+
if (shouldEliminate) {
2581+
ReplaceUses(SDValue(Node, 0), Node->getOperand(0));
2582+
CurDAG->RemoveDeadNode(Node);
2583+
return;
2584+
}
2585+
}
25692586
break;
25702587
}
25712588
case ISD::INSERT_SUBVECTOR:

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -279,6 +279,18 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
279279
addRegisterClass(MVT::riscv_nxv32i8x2, &RISCV::VRN2M4RegClass);
280280
}
281281

282+
// fixed vector is stored in GPRs for P extension packed operations
283+
if (Subtarget.hasStdExtP()) {
284+
if (Subtarget.is64Bit()) {
285+
addRegisterClass(MVT::v2i32, &RISCV::GPRRegClass);
286+
addRegisterClass(MVT::v4i16, &RISCV::GPRRegClass);
287+
addRegisterClass(MVT::v8i8, &RISCV::GPRRegClass);
288+
} else {
289+
addRegisterClass(MVT::v2i16, &RISCV::GPRRegClass);
290+
addRegisterClass(MVT::v4i8, &RISCV::GPRRegClass);
291+
}
292+
}
293+
282294
// Compute derived properties from the register classes.
283295
computeRegisterProperties(STI.getRegisterInfo());
284296

@@ -485,6 +497,36 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
485497
ISD::FTRUNC, ISD::FRINT, ISD::FROUND,
486498
ISD::FROUNDEVEN, ISD::FCANONICALIZE};
487499

500+
if (Subtarget.hasStdExtP()) {
501+
// load/store are already handled by pattern matching
502+
if (Subtarget.is64Bit()) {
503+
for (auto VT : {MVT::v4i16, MVT::v8i8}) {
504+
setOperationAction(ISD::UADDSAT, VT, Legal);
505+
setOperationAction(ISD::SADDSAT, VT, Legal);
506+
setOperationAction(ISD::USUBSAT, VT, Legal);
507+
setOperationAction(ISD::SSUBSAT, VT, Legal);
508+
setOperationAction(ISD::SSHLSAT, VT, Legal);
509+
setOperationAction(ISD::USHLSAT, VT, Legal);
510+
setOperationAction(ISD::BITCAST, VT, Custom);
511+
setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, VT, Legal);
512+
setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal);
513+
}
514+
setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
515+
} else {
516+
for (auto VT : {MVT::v2i16, MVT::v4i8}) {
517+
setOperationAction(ISD::UADDSAT, VT, Legal);
518+
setOperationAction(ISD::SADDSAT, VT, Legal);
519+
setOperationAction(ISD::USUBSAT, VT, Legal);
520+
setOperationAction(ISD::SSUBSAT, VT, Legal);
521+
setOperationAction(ISD::SSHLSAT, VT, Legal);
522+
setOperationAction(ISD::USHLSAT, VT, Legal);
523+
setOperationAction(ISD::BITCAST, VT, Custom);
524+
setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, VT, Legal);
525+
setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal);
526+
}
527+
}
528+
}
529+
488530
if (Subtarget.hasStdExtZfbfmin()) {
489531
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
490532
setOperationAction(ISD::ConstantFP, MVT::bf16, Expand);
@@ -7455,6 +7497,14 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
74557497
assert(!VT.isScalableVector() && !Op0VT.isScalableVector() &&
74567498
"Unexpected types");
74577499

7500+
// Special case: bitcast between i64 and v4i16 when both use GPRs (P extension)
7501+
if (Subtarget.is64Bit() && Subtarget.hasStdExtP() &&
7502+
((VT == MVT::v4i16 && Op0VT == MVT::i64) ||
7503+
(VT == MVT::i64 && Op0VT == MVT::v4i16))) {
7504+
// Both types use the same GPR register class, so this is a no-op
7505+
return Op;
7506+
}
7507+
74587508
if (VT.isFixedLengthVector()) {
74597509
// We can handle fixed length vector bitcasts with a simple replacement
74607510
// in isel.

‎llvm/lib/Target/RISCV/RISCVInstrInfoP.td‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -542,6 +542,8 @@ let Predicates = [HasStdExtP] in {
542542
def PASUBU_H : RVPBinary_rr<0b1111, 0b00, 0b000, "pasubu.h">;
543543
def PASUBU_B : RVPBinary_rr<0b1111, 0b10, 0b000, "pasubu.b">;
544544
} // Predicates = [HasStdExtP]
545+
546+
545547
let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
546548
def SADD : RVPBinary_rr<0b0010, 0b01, 0b000, "sadd">;
547549

@@ -1197,3 +1199,127 @@ let Predicates = [HasStdExtP, IsRV32] in {
11971199
def PNCLIPR_HS : RVPNarrowingShift_rr<0b111, 0b01, "pnclipr.hs">;
11981200
def NCLIPR : RVPNarrowingShift_rr<0b111, 0b11, "nclipr">;
11991201
} // Predicates = [HasStdExtP, IsRV32]
1202+
1203+
let Predicates = [HasStdExtP, IsRV64] in {
1204+
// Basic arithmetic patterns for v4i16 (16-bit elements in 64-bit GPR)
1205+
def: Pat<(v4i16 (add v4i16:$rs1, v4i16:$rs2)), (!cast<Instruction>("PADD_H") GPR:$rs1, GPR:$rs2)>;
1206+
def: Pat<(v4i16 (sub v4i16:$rs1, v4i16:$rs2)), (!cast<Instruction>("PSUB_H") GPR:$rs1, GPR:$rs2)>;
1207+
1208+
// Saturating add/sub patterns for v4i16
1209+
def: Pat<(v4i16 (saddsat v4i16:$rs1, v4i16:$rs2)), (!cast<Instruction>("PSADD_H") GPR:$rs1, GPR:$rs2)>;
1210+
def: Pat<(v4i16 (uaddsat v4i16:$rs1, v4i16:$rs2)), (!cast<Instruction>("PSADDU_H") GPR:$rs1, GPR:$rs2)>;
1211+
def: Pat<(v4i16 (ssubsat v4i16:$rs1, v4i16:$rs2)), (!cast<Instruction>("PSSUB_H") GPR:$rs1, GPR:$rs2)>;
1212+
def: Pat<(v4i16 (usubsat v4i16:$rs1, v4i16:$rs2)), (!cast<Instruction>("PSSUBU_H") GPR:$rs1, GPR:$rs2)>;
1213+
1214+
// Averaging patterns for v4i16
1215+
def: Pat<(v4i16 (avgfloors v4i16:$rs1, v4i16:$rs2)), (!cast<Instruction>("PAADD_H") GPR:$rs1, GPR:$rs2)>;
1216+
def: Pat<(v4i16 (avgflooru v4i16:$rs1, v4i16:$rs2)), (!cast<Instruction>("PAADDU_H") GPR:$rs1, GPR:$rs2)>;
1217+
1218+
// Averaging subtraction patterns for v4i16
1219+
// PASUB_H: signed (a - b) >> 1
1220+
def: Pat<(v4i16 (sra (sub v4i16:$rs1, v4i16:$rs2), (v4i16 (build_vector (XLenVT 1))))),
1221+
(!cast<Instruction>("PASUB_H") GPR:$rs1, GPR:$rs2)>;
1222+
// PASUBU_H: unsigned (a - b) >> 1
1223+
def: Pat<(v4i16 (srl (sub v4i16:$rs1, v4i16:$rs2), (v4i16 (build_vector (XLenVT 1))))),
1224+
(!cast<Instruction>("PASUBU_H") GPR:$rs1, GPR:$rs2)>;
1225+
1226+
// Absolute difference patterns for v4i16
1227+
def: Pat<(v4i16 (abds v4i16:$rs1, v4i16:$rs2)), (!cast<Instruction>("PDIF_H") GPR:$rs1, GPR:$rs2)>;
1228+
def: Pat<(v4i16 (abdu v4i16:$rs1, v4i16:$rs2)), (!cast<Instruction>("PDIFU_H") GPR:$rs1, GPR:$rs2)>;
1229+
1230+
// Basic arithmetic patterns for v8i8 (8-bit elements in 64-bit GPR)
1231+
def: Pat<(v8i8 (add v8i8:$rs1, v8i8:$rs2)), (!cast<Instruction>("PADD_B") GPR:$rs1, GPR:$rs2)>;
1232+
def: Pat<(v8i8 (sub v8i8:$rs1, v8i8:$rs2)), (!cast<Instruction>("PSUB_B") GPR:$rs1, GPR:$rs2)>;
1233+
1234+
// Saturating add/sub patterns for v8i8
1235+
def: Pat<(v8i8 (saddsat v8i8:$rs1, v8i8:$rs2)), (!cast<Instruction>("PSADD_B") GPR:$rs1, GPR:$rs2)>;
1236+
def: Pat<(v8i8 (uaddsat v8i8:$rs1, v8i8:$rs2)), (!cast<Instruction>("PSADDU_B") GPR:$rs1, GPR:$rs2)>;
1237+
def: Pat<(v8i8 (ssubsat v8i8:$rs1, v8i8:$rs2)), (!cast<Instruction>("PSSUB_B") GPR:$rs1, GPR:$rs2)>;
1238+
def: Pat<(v8i8 (usubsat v8i8:$rs1, v8i8:$rs2)), (!cast<Instruction>("PSSUBU_B") GPR:$rs1, GPR:$rs2)>;
1239+
1240+
// Averaging patterns for v8i8
1241+
def: Pat<(v8i8 (avgfloors v8i8:$rs1, v8i8:$rs2)), (!cast<Instruction>("PAADD_B") GPR:$rs1, GPR:$rs2)>;
1242+
def: Pat<(v8i8 (avgflooru v8i8:$rs1, v8i8:$rs2)), (!cast<Instruction>("PAADDU_B") GPR:$rs1, GPR:$rs2)>;
1243+
1244+
// Averaging subtraction patterns for v8i8
1245+
// PASUB_B: signed (a - b) >> 1
1246+
def: Pat<(v8i8 (sra (sub v8i8:$rs1, v8i8:$rs2), (v8i8 (build_vector (XLenVT 1))))),
1247+
(!cast<Instruction>("PASUB_B") GPR:$rs1, GPR:$rs2)>;
1248+
// PASUBU_B: unsigned (a - b) >> 1
1249+
def: Pat<(v8i8 (srl (sub v8i8:$rs1, v8i8:$rs2), (v8i8 (build_vector (XLenVT 1))))),
1250+
(!cast<Instruction>("PASUBU_B") GPR:$rs1, GPR:$rs2)>;
1251+
1252+
// Absolute difference patterns for v8i8
1253+
def: Pat<(v8i8 (abds v8i8:$rs1, v8i8:$rs2)), (!cast<Instruction>("PDIF_B") GPR:$rs1, GPR:$rs2)>;
1254+
def: Pat<(v8i8 (abdu v8i8:$rs1, v8i8:$rs2)), (!cast<Instruction>("PDIFU_B") GPR:$rs1, GPR:$rs2)>;
1255+
1256+
// Load/Store patterns for v4i16 and v8i8 (use regular GPR load/store since they're in GPRs)
1257+
def : StPat<store, SD, GPR, v4i16>;
1258+
def : LdPat<load, LD, v4i16>;
1259+
def : StPat<store, SD, GPR, v8i8>;
1260+
def : LdPat<load, LD, v8i8>;
1261+
1262+
// Load/Store patterns for v2i32 (32-bit elements in 64-bit GPR)
1263+
def : StPat<store, SD, GPR, v2i32>;
1264+
def : LdPat<load, LD, v2i32>;
1265+
} // Predicates = [HasStdExtP, IsRV64]
1266+
1267+
let Predicates = [HasStdExtP, IsRV32] in {
1268+
// Basic arithmetic patterns for v2i16 (16-bit elements in 32-bit GPR)
1269+
def: Pat<(v2i16 (add v2i16:$rs1, v2i16:$rs2)), (!cast<Instruction>("PADD_H") GPR:$rs1, GPR:$rs2)>;
1270+
def: Pat<(v2i16 (sub v2i16:$rs1, v2i16:$rs2)), (!cast<Instruction>("PSUB_H") GPR:$rs1, GPR:$rs2)>;
1271+
1272+
// Saturating add/sub patterns for v2i16
1273+
def: Pat<(v2i16 (saddsat v2i16:$rs1, v2i16:$rs2)), (!cast<Instruction>("PSADD_H") GPR:$rs1, GPR:$rs2)>;
1274+
def: Pat<(v2i16 (uaddsat v2i16:$rs1, v2i16:$rs2)), (!cast<Instruction>("PSADDU_H") GPR:$rs1, GPR:$rs2)>;
1275+
def: Pat<(v2i16 (ssubsat v2i16:$rs1, v2i16:$rs2)), (!cast<Instruction>("PSSUB_H") GPR:$rs1, GPR:$rs2)>;
1276+
def: Pat<(v2i16 (usubsat v2i16:$rs1, v2i16:$rs2)), (!cast<Instruction>("PSSUBU_H") GPR:$rs1, GPR:$rs2)>;
1277+
1278+
// Averaging patterns for v2i16
1279+
def: Pat<(v2i16 (avgfloors v2i16:$rs1, v2i16:$rs2)), (!cast<Instruction>("PAADD_H") GPR:$rs1, GPR:$rs2)>;
1280+
def: Pat<(v2i16 (avgflooru v2i16:$rs1, v2i16:$rs2)), (!cast<Instruction>("PAADDU_H") GPR:$rs1, GPR:$rs2)>;
1281+
1282+
// Averaging subtraction patterns for v2i16
1283+
// PASUB_H: signed (a - b) >> 1
1284+
def: Pat<(v2i16 (sra (sub v2i16:$rs1, v2i16:$rs2), (v2i16 (build_vector (XLenVT 1))))),
1285+
(!cast<Instruction>("PASUB_H") GPR:$rs1, GPR:$rs2)>;
1286+
// PASUBU_H: unsigned (a - b) >> 1
1287+
def: Pat<(v2i16 (srl (sub v2i16:$rs1, v2i16:$rs2), (v2i16 (build_vector (XLenVT 1))))),
1288+
(!cast<Instruction>("PASUBU_H") GPR:$rs1, GPR:$rs2)>;
1289+
1290+
// Absolute difference patterns for v2i16
1291+
def: Pat<(v2i16 (abds v2i16:$rs1, v2i16:$rs2)), (!cast<Instruction>("PDIF_H") GPR:$rs1, GPR:$rs2)>;
1292+
def: Pat<(v2i16 (abdu v2i16:$rs1, v2i16:$rs2)), (!cast<Instruction>("PDIFU_H") GPR:$rs1, GPR:$rs2)>;
1293+
1294+
// Basic arithmetic patterns for v4i8 (8-bit elements in 32-bit GPR)
1295+
def: Pat<(v4i8 (add v4i8:$rs1, v4i8:$rs2)), (!cast<Instruction>("PADD_B") GPR:$rs1, GPR:$rs2)>;
1296+
def: Pat<(v4i8 (sub v4i8:$rs1, v4i8:$rs2)), (!cast<Instruction>("PSUB_B") GPR:$rs1, GPR:$rs2)>;
1297+
1298+
// Saturating add/sub patterns for v4i8
1299+
def: Pat<(v4i8 (saddsat v4i8:$rs1, v4i8:$rs2)), (!cast<Instruction>("PSADD_B") GPR:$rs1, GPR:$rs2)>;
1300+
def: Pat<(v4i8 (uaddsat v4i8:$rs1, v4i8:$rs2)), (!cast<Instruction>("PSADDU_B") GPR:$rs1, GPR:$rs2)>;
1301+
def: Pat<(v4i8 (ssubsat v4i8:$rs1, v4i8:$rs2)), (!cast<Instruction>("PSSUB_B") GPR:$rs1, GPR:$rs2)>;
1302+
def: Pat<(v4i8 (usubsat v4i8:$rs1, v4i8:$rs2)), (!cast<Instruction>("PSSUBU_B") GPR:$rs1, GPR:$rs2)>;
1303+
1304+
// Averaging patterns for v4i8
1305+
def: Pat<(v4i8 (avgfloors v4i8:$rs1, v4i8:$rs2)), (!cast<Instruction>("PAADD_B") GPR:$rs1, GPR:$rs2)>;
1306+
def: Pat<(v4i8 (avgflooru v4i8:$rs1, v4i8:$rs2)), (!cast<Instruction>("PAADDU_B") GPR:$rs1, GPR:$rs2)>;
1307+
1308+
// Averaging subtraction patterns for v4i8
1309+
// PASUB_B: signed (a - b) >> 1
1310+
def: Pat<(v4i8 (sra (sub v4i8:$rs1, v4i8:$rs2), (v4i8 (build_vector (XLenVT 1))))),
1311+
(!cast<Instruction>("PASUB_B") GPR:$rs1, GPR:$rs2)>;
1312+
// PASUBU_B: unsigned (a - b) >> 1
1313+
def: Pat<(v4i8 (srl (sub v4i8:$rs1, v4i8:$rs2), (v4i8 (build_vector (XLenVT 1))))),
1314+
(!cast<Instruction>("PASUBU_B") GPR:$rs1, GPR:$rs2)>;
1315+
1316+
// Absolute difference patterns for v4i8
1317+
def: Pat<(v4i8 (abds v4i8:$rs1, v4i8:$rs2)), (!cast<Instruction>("PDIF_B") GPR:$rs1, GPR:$rs2)>;
1318+
def: Pat<(v4i8 (abdu v4i8:$rs1, v4i8:$rs2)), (!cast<Instruction>("PDIFU_B") GPR:$rs1, GPR:$rs2)>;
1319+
1320+
// Load/Store patterns for v2i16 and v4i8 (use regular GPR load/store since they're in GPRs)
1321+
def : StPat<store, SW, GPR, v2i16>;
1322+
def : LdPat<load, LW, v2i16>;
1323+
def : StPat<store, SW, GPR, v4i8>;
1324+
def : LdPat<load, LW, v4i8>;
1325+
} // Predicates = [HasStdExtP, IsRV32]

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -238,7 +238,11 @@ class RISCVRegisterClass<list<ValueType> regTypes, int align, dag regList>
238238
}
239239

240240
class GPRRegisterClass<dag regList>
241-
: RISCVRegisterClass<[XLenVT, XLenFVT, i32, i16], 32, regList> {
241+
: RISCVRegisterClass<[XLenVT, XLenFVT, i32, i16,
242+
// P extension packed vector types:
243+
// RV32: v2i16, v4i8
244+
// RV64: v2i32, v4i16, v8i8
245+
v2i16, v4i8, v2i32, v4i16, v8i8], 32, regList> {
242246
let RegInfos = XLenRI;
243247
}
244248

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -931,6 +931,13 @@ InstructionCost RISCVTTIImpl::getScalarizationOverhead(
931931
if (isa<ScalableVectorType>(Ty))
932932
return InstructionCost::getInvalid();
933933

934+
// TODO: Add proper cost model for P extension fixed vectors (e.g., v4i16)
935+
// For now, skip all fixed vector cost analysis when P extension is available
936+
// to avoid crashes in getMinRVVVectorSizeInBits()
937+
if (ST->hasStdExtP() && isa<FixedVectorType>(Ty)) {
938+
return 1; // Treat as single instruction cost for now
939+
}
940+
934941
// A build_vector (which is m1 sized or smaller) can be done in no
935942
// worse than one vslide1down.vx per element in the type. We could
936943
// in theory do an explode_vector in the inverse manner, but our
@@ -1587,6 +1594,13 @@ InstructionCost RISCVTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
15871594
if (!IsVectorType)
15881595
return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
15891596

1597+
// TODO: Add proper cost model for P extension fixed vectors (e.g., v4i16)
1598+
// For now, skip all fixed vector cost analysis when P extension is available
1599+
// to avoid crashes in getMinRVVVectorSizeInBits()
1600+
if (ST->hasStdExtP() && (isa<FixedVectorType>(Dst) || isa<FixedVectorType>(Src))) {
1601+
return 1; // Treat as single instruction cost for now
1602+
}
1603+
15901604
// FIXME: Need to compute legalizing cost for illegal types. The current
15911605
// code handles only legal types and those which can be trivially
15921606
// promoted to legal.
@@ -2283,6 +2297,13 @@ InstructionCost RISCVTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
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const Value *Op1) const {
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assert(Val->isVectorTy() && "This must be a vector type");
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// TODO: Add proper cost model for P extension fixed vectors (e.g., v4i16)
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// For now, skip all fixed vector cost analysis when P extension is available
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// to avoid crashes in getMinRVVVectorSizeInBits()
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if (ST->hasStdExtP() && isa<FixedVectorType>(Val)) {
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return 1; // Treat as single instruction cost for now
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}
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if (Opcode != Instruction::ExtractElement &&
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Opcode != Instruction::InsertElement)
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return BaseT::getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1);

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