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[PowerPC] Add intrinsic definition for load and store with Right Length Left-justified (#148873)
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‎llvm/include/llvm/IR/IntrinsicsPowerPC.td‎

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@@ -1358,6 +1358,18 @@ def int_ppc_vsx_lxvll :
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def int_ppc_vsx_lxvp :
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DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty],
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[IntrReadMem, IntrArgMemOnly]>;
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def int_ppc_vsx_lxvrl :
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DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty],
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[IntrReadMem, IntrArgMemOnly]>;
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def int_ppc_vsx_lxvrll :
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DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty],
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[IntrReadMem, IntrArgMemOnly]>;
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def int_ppc_vsx_lxvprl :
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DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty, llvm_i64_ty],
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[IntrReadMem, IntrArgMemOnly]>;
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def int_ppc_vsx_lxvprll :
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DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty, llvm_i64_ty],
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[IntrReadMem, IntrArgMemOnly]>;
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// Vector store.
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def int_ppc_vsx_stxvw4x : Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
@@ -1377,6 +1389,19 @@ def int_ppc_vsx_stxvll :
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def int_ppc_vsx_stxvp :
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Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty], [IntrWriteMem,
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IntrArgMemOnly]>;
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def int_ppc_vsx_stxvrl :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
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[IntrWriteMem, IntrArgMemOnly]>;
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def int_ppc_vsx_stxvrll :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
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[IntrWriteMem, IntrArgMemOnly]>;
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def int_ppc_vsx_stxvprl :
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Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem,
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IntrArgMemOnly]>;
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def int_ppc_vsx_stxvprll :
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Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem,
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IntrArgMemOnly]>;
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// Vector and scalar maximum.
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def int_ppc_vsx_xvmaxdp : PowerPC_VSX_Vec_DDD_Intrinsic<"xvmaxdp">;
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def int_ppc_vsx_xvmaxsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvmaxsp">;

‎llvm/lib/Target/PowerPC/PPCInstrFuture.td‎

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@@ -192,3 +192,21 @@ let Predicates = [HasVSX, IsISAFuture] in {
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: VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
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"vucmprlh $VRT, $VRA, $VRB", []>;
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}
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//---------------------------- Anonymous Patterns ----------------------------//
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// Load/Store VSX Vector with Right Length (Left-justified).
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def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
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def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
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def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB), (STXVRL $XT, $RA,
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$RB)>;
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def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB), (STXVRLL $XT, $RA,
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$RB)>;
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// Load/Store VSX Vector pair with Right Length (Left-justified).
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def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
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def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
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def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRL $XTp,
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$RA, $RB)>;
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def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp,
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$RA, $RB)>;

‎llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll‎

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@@ -0,0 +1,157 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
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; RUN: FileCheck %s --check-prefix=AIX
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; Test for load/store to/from v4i32.
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define <4 x i32> @testLXVRL(ptr %a, i64 %b) {
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; CHECK-LABEL: testLXVRL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvrl v2, r3, r4
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testLXVRL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxvrl v2, r3, r4
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; AIX-NEXT: blr
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrl(ptr %a, i64 %b)
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ret <4 x i32> %0
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}
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declare <4 x i32> @llvm.ppc.vsx.lxvrl(ptr, i64)
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define <4 x i32> @testLXVRLL(ptr %a, i64 %b) {
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; CHECK-LABEL: testLXVRLL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvrll v2, r3, r4
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testLXVRLL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxvrll v2, r3, r4
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; AIX-NEXT: blr
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrll(ptr %a, i64 %b)
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ret <4 x i32> %0
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}
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declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
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define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
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; CHECK-LABEL: testSTXVRL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stxvrl v2, r5, r6
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testSTXVRL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: stxvrl v2, r3, r4
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; AIX-NEXT: blr
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entry:
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tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
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ret void
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}
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declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
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define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
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; CHECK-LABEL: testSTXVRLL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stxvrll v2, r5, r6
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testSTXVRLL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: stxvrll v2, r3, r4
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; AIX-NEXT: blr
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entry:
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tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
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ret void
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}
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declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
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; Test for load/store vectore pair.
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define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
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; CHECK-LABEL: testLXVPRL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvprl vsp34, r4, r5
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; CHECK-NEXT: stxv v2, 16(r3)
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; CHECK-NEXT: stxv v3, 0(r3)
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testLXVPRL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxvprl vsp34, r4, r5
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; AIX-NEXT: stxv v3, 16(r3)
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; AIX-NEXT: stxv v2, 0(r3)
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; AIX-NEXT: blr
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entry:
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%0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
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ret <256 x i1> %0
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}
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declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
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define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
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; CHECK-LABEL: testLXVPRLL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvprll vsp34, r4, r5
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; CHECK-NEXT: stxv v2, 16(r3)
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; CHECK-NEXT: stxv v3, 0(r3)
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testLXVPRLL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxvprll vsp34, r4, r5
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; AIX-NEXT: stxv v3, 16(r3)
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; AIX-NEXT: stxv v2, 0(r3)
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; AIX-NEXT: blr
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entry:
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%0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
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ret <256 x i1> %0
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}
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declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
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define void @testSTXVPRL(ptr %v, ptr %vp, i64 %len) {
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; CHECK-LABEL: testSTXVPRL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv v2, 16(r3)
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; CHECK-NEXT: lxv v3, 0(r3)
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; CHECK-NEXT: stxvprl vsp34, r4, r5
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testSTXVPRL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxv v2, 0(r3)
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; AIX-NEXT: lxv v3, 16(r3)
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; AIX-NEXT: stxvprl vsp34, r4, r5
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; AIX-NEXT: blr
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entry:
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%0 = load <256 x i1>, ptr %v, align 32
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tail call void @llvm.ppc.vsx.stxvprl(<256 x i1> %0, ptr %vp, i64 %len)
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ret void
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}
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declare void @llvm.ppc.vsx.stxvprl(<256 x i1>, ptr, i64)
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define void @testSTXVPRLL(ptr %v, ptr %vp, i64 %len) {
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; CHECK-LABEL: testSTXVPRLL:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv v2, 16(r3)
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; CHECK-NEXT: lxv v3, 0(r3)
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; CHECK-NEXT: stxvprll vsp34, r4, r5
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; CHECK-NEXT: blr
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;
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; AIX-LABEL: testSTXVPRLL:
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; AIX: # %bb.0: # %entry
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; AIX-NEXT: lxv v2, 0(r3)
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; AIX-NEXT: lxv v3, 16(r3)
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; AIX-NEXT: stxvprll vsp34, r4, r5
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; AIX-NEXT: blr
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entry:
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%0 = load <256 x i1>, ptr %v, align 32
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tail call void @llvm.ppc.vsx.stxvprll(<256 x i1> %0, ptr %vp, i64 %len)
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ret void
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}
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declare void @llvm.ppc.vsx.stxvprll(<256 x i1>, ptr, i64)

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