Add other instructions & fix typo

Created using spr 1.3.5

Author: koachan

llvm/lib/Target/Sparc/SparcInstrUAOSA.td

@@ -1,4 +1,4 @@
-//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
+//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions ===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -18,4 +18,19 @@ def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
     let Inst{29-19} = 0b00010110001;
     let Inst{18-0} = 0;
 }
+def INVALW : InstSP<(outs), (ins), "invalw", []> {
+    let op = 2;
+    let Inst{29-19} = 0b00101110001;
+    let Inst{18-0} = 0;
+}
+def NORMALW : InstSP<(outs), (ins), "normalw", []> {
+    let op = 2;
+    let Inst{29-19} = 0b00100110001;
+    let Inst{18-0} = 0;
+}
+def OTHERW : InstSP<(outs), (ins), "otherw", []> {
+    let op = 2;
+    let Inst{29-19} = 0b00011110001;
+    let Inst{18-0} = 0;
+}
 } // Predicates = [HasUA2005]

llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt

@@ -4,3 +4,9 @@
 
 # CHECK: allclean
 0x85,0x88,0x00,0x00
+# CHECK: invalw
+0x8b,0x88,0x00,0x00
+# CHECK: otherw
+0x87,0x88,0x00,0x00
+# CHECK: normalw
+0x89,0x88,0x00,0x00

llvm/test/MC/Sparc/sparc-ua2005.s

@@ -6,3 +6,12 @@
 ! NO-UA2005: error: instruction requires a CPU feature not currently enabled
 ! UA2005: allclean                   ! encoding: [0x85,0x88,0x00,0x00]
 allclean
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: invalw                     ! encoding: [0x8b,0x88,0x00,0x00]
+invalw
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: otherw                     ! encoding: [0x87,0x88,0x00,0x00]
+otherw
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: normalw                    ! encoding: [0x89,0x88,0x00,0x00]
+normalw