Handle non neg case

Author: ningxinr

llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp

@@ -1960,17 +1960,38 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
     break;
   }
   case TargetOpcode::G_ADD: {
+    Register Src2 = MI.getOperand(2).getReg();
+    unsigned Src2NumSignBits =
+        computeNumSignBits(Src2, DemandedElts, Depth + 1);
+    if (Src2NumSignBits == 1)
+      return 1; // Early out.
+
     Register Src1 = MI.getOperand(1).getReg();
     unsigned Src1NumSignBits =
         computeNumSignBits(Src1, DemandedElts, Depth + 1);
-    if (Src1NumSignBits != 1) {
-      Register Src2 = MI.getOperand(2).getReg();
-      unsigned Src2NumSignBits =
-          computeNumSignBits(Src2, DemandedElts, Depth + 1);
-      if (Src2NumSignBits == 1)
-        return 1; // Early out.
-      FirstAnswer = std::min(Src1NumSignBits, Src2NumSignBits) - 1;
+    if (Src1NumSignBits == 1)
+      return 1; // Early Out.
+
+    // Special case decrementing a value (ADD X, -1):
+    KnownBits Known2 = getKnownBits(Src2, DemandedElts, Depth);
+    if (Known2.isAllOnes()) {
+      KnownBits Known1 = getKnownBits(Src1, DemandedElts, Depth);
+      // If the input is known to be 0 or 1, the output is 0/-1, which is all
+      // sign bits set.
+      if ((Known1.Zero | 1).isAllOnes())
+        return TyBits;
+
+      // If the input is known to be positive (the sign bit is known clear),
+      // the output of the NEG has the same number of sign bits as the input.
+      if (Known1.isNonNegative())
+        return Src1NumSignBits;
+
+      // Otherwise, we treat this like an ADD.
     }
+
+    // Add can have at most one carry bit.  Thus we know that the output
+    // is, at worst, one more bit than the inputs.
+    FirstAnswer = std::min(Src1NumSignBits, Src2NumSignBits) - 1;
     break;
   }
   case TargetOpcode::G_FCMP:

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -5058,8 +5058,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
     break;
   case ISD::ADD:
   case ISD::ADDC:
-    // Add can have at most one carry bit.  Thus we know that the output
-    // is, at worst, one more bit than the inputs.
+    // TODO: Move Operand 1 check before Operand 0 check
     Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
     if (Tmp == 1) return 1; // Early out.
 
@@ -5083,6 +5082,9 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
 
     Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);
     if (Tmp2 == 1) return 1; // Early out.
+
+    // Add can have at most one carry bit.  Thus we know that the output
+    // is, at worst, one more bit than the inputs.
     return std::min(Tmp, Tmp2) - 1;
   case ISD::SUB:
     Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedElts, Depth + 1);

llvm/test/CodeGen/AArch64/GlobalISel/knownbits-add.mir

@@ -82,7 +82,7 @@ body:             |
   ; CHECK-NEXT: %1:_ KnownBits:00001111 SignBits:4
   ; CHECK-NEXT: %2:_ KnownBits:0000???? SignBits:4
   ; CHECK-NEXT: %3:_ KnownBits:11111111 SignBits:8
-  ; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:3
+  ; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:4
     %0:_(s8) = COPY $b0
     %1:_(s8) = G_CONSTANT i8 15
     %2:_(s8) = G_AND %0, %1
@@ -154,7 +154,7 @@ body:             |
   ; CHECK-NEXT: %3:_ KnownBits:00000000???????? SignBits:8
   ; CHECK-NEXT: %4:_ KnownBits:1111111111111111 SignBits:16
   ; CHECK-NEXT: %5:_ KnownBits:1111111111111111 SignBits:16
-  ; CHECK-NEXT: %6:_ KnownBits:???????????????? SignBits:7
+  ; CHECK-NEXT: %6:_ KnownBits:???????????????? SignBits:8
     %0:_(<4 x s16>) = COPY $d0
     %1:_(s16) = G_CONSTANT i16 255
     %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1