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Add add_uxtx complex pattern, SUBXrr -> SUBXrx64, re-generate mingw-refptr.ll
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7 files changed

+66
-84
lines changed

7 files changed

+66
-84
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAG.h‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -853,10 +853,6 @@ class SelectionDAG {
853853
ArrayRef(Ops, Glue.getNode() ? 3 : 2));
854854
}
855855

856-
SDValue getAddToReg(const SDLoc &dl, Register Reg, EVT VT, SDValue Delta) {
857-
return getNode(ISD::ADD, dl, VT, getRegister(Reg, VT), Delta);
858-
}
859-
860856
LLVM_ABI SDValue getCondCode(ISD::CondCode Cond);
861857

862858
/// Return an ISD::VECTOR_SHUFFLE node. The number of elements in VT,

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,8 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
7474
template <signed Low, signed High>
7575
bool SelectRDSVLShiftImm(SDValue N, SDValue &Imm);
7676

77+
bool SelectAddUXTXRegister(SDValue N, SDValue &Reg, SDValue &Shift);
78+
7779
bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
7880
bool SelectArithUXTXRegister(SDValue N, SDValue &Reg, SDValue &Shift);
7981
bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
@@ -959,6 +961,18 @@ bool AArch64DAGToDAGISel::SelectRDSVLShiftImm(SDValue N, SDValue &Imm) {
959961
return false;
960962
}
961963

964+
/// SelectAddUXTXRegister - Select a "UXTX register" operand. This
965+
/// operand is referred by the instructions have SP operand
966+
bool AArch64DAGToDAGISel::SelectAddUXTXRegister(SDValue N, SDValue &Reg,
967+
SDValue &Shift) {
968+
if (N.getOpcode() != ISD::LOAD)
969+
return false;
970+
Reg = N;
971+
Shift = CurDAG->getTargetConstant(getArithExtendImm(AArch64_AM::UXTX, 0),
972+
SDLoc(N), MVT::i32);
973+
return true;
974+
}
975+
962976
/// SelectArithExtendedRegister - Select a "extended register" operand. This
963977
/// operand folds in an extend followed by an optional left shift.
964978
bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29252,10 +29252,12 @@ SDValue AArch64TargetLowering::emitStackGuardMixCookie(SelectionDAG &DAG,
2925229252
SDValue Val,
2925329253
const SDLoc &DL,
2925429254
bool FailureBB) const {
29255-
if (FailureBB) {
29256-
return DAG.getAddToReg(DL, getStackPointerRegisterToSaveRestore(), MVT::i64,
29257-
Val);
29258-
}
29255+
if (FailureBB)
29256+
return DAG.getNode(
29257+
ISD::ADD, DL, Val.getValueType(),
29258+
DAG.getCopyFromReg(DAG.getEntryNode(), DL,
29259+
getStackPointerRegisterToSaveRestore(), MVT::i64),
29260+
Val);
2925929261
return Val;
2926029262
}
2926129263

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1386,6 +1386,8 @@ def gi_arith_extended_reg32to64_i64 :
13861386

13871387
def arith_uxtx : ComplexPattern<i64, 2, "SelectArithUXTXRegister", []>;
13881388

1389+
def add_uxtx : ComplexPattern<i64, 2, "SelectAddUXTXRegister", []>;
1390+
13891391
// Floating-point immediate.
13901392

13911393
def fpimm16XForm : SDNodeXForm<fpimm, [{

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2502,9 +2502,10 @@ bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
25022502
!Subtarget.getTargetLowering()
25032503
->getTargetMachine()
25042504
.Options.EnableGlobalISel) {
2505-
BuildMI(MBB, MI, DL, get(AArch64::SUBXrr), Reg)
2505+
BuildMI(MBB, MI, DL, get(AArch64::SUBXrx64), Reg)
25062506
.addReg(AArch64::SP)
2507-
.addReg(Reg, RegState::Kill);
2507+
.addReg(Reg, RegState::Kill)
2508+
.addImm(AArch64_AM::getArithExtendImm(AArch64_AM::UXTX, 0));
25082509
}
25092510

25102511
MBB.erase(MI);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2752,6 +2752,11 @@ def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
27522752
(ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
27532753
}
27542754

2755+
let AddedComplexity = 1 in {
2756+
def : Pat<(add copyFromSP:$R2, (add_uxtx GPR64:$R3, arith_extendlsl64:$imm)),
2757+
(ADDXrx64 GPR64sp:$R2, GPR64:$R3, arith_extendlsl64:$imm)>;
2758+
}
2759+
27552760
def : InstAlias<"neg $dst, $src",
27562761
(SUBWrs GPR32:$dst, WZR,
27572762
(arith_shifted_reg32 GPR32:$src, 0)), 3>;

‎llvm/test/CodeGen/AArch64/mingw-refptr.ll‎

Lines changed: 36 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22
; RUN: llc < %s -mtriple=aarch64-w64-mingw32 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3-
; RUN: llc < %s -mtriple=aarch64-w64-mingw32 -global-isel | FileCheck %s --check-prefixes=CHECK-GI
3+
; RUN: llc < %s -mtriple=aarch64-w64-mingw32 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
@var = external local_unnamed_addr global i32, align 4
66
@dsolocalvar = external dso_local local_unnamed_addr global i32, align 4
@@ -15,13 +15,6 @@ define dso_local i32 @getVar() {
1515
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.var]
1616
; CHECK-NEXT: ldr w0, [x8]
1717
; CHECK-NEXT: ret
18-
;
19-
; CHECK-GI-LABEL: getVar:
20-
; CHECK-GI: // %bb.0: // %entry
21-
; CHECK-GI-NEXT: adrp x8, .refptr.var
22-
; CHECK-GI-NEXT: ldr x8, [x8, :lo12:.refptr.var]
23-
; CHECK-GI-NEXT: ldr w0, [x8]
24-
; CHECK-GI-NEXT: ret
2518
entry:
2619
%0 = load i32, ptr @var, align 4
2720
ret i32 %0
@@ -33,12 +26,6 @@ define dso_local i32 @getDsoLocalVar() {
3326
; CHECK-NEXT: adrp x8, dsolocalvar
3427
; CHECK-NEXT: ldr w0, [x8, :lo12:dsolocalvar]
3528
; CHECK-NEXT: ret
36-
;
37-
; CHECK-GI-LABEL: getDsoLocalVar:
38-
; CHECK-GI: // %bb.0: // %entry
39-
; CHECK-GI-NEXT: adrp x8, dsolocalvar
40-
; CHECK-GI-NEXT: ldr w0, [x8, :lo12:dsolocalvar]
41-
; CHECK-GI-NEXT: ret
4229
entry:
4330
%0 = load i32, ptr @dsolocalvar, align 4
4431
ret i32 %0
@@ -50,12 +37,6 @@ define dso_local i32 @getLocalVar() {
5037
; CHECK-NEXT: adrp x8, localvar
5138
; CHECK-NEXT: ldr w0, [x8, :lo12:localvar]
5239
; CHECK-NEXT: ret
53-
;
54-
; CHECK-GI-LABEL: getLocalVar:
55-
; CHECK-GI: // %bb.0: // %entry
56-
; CHECK-GI-NEXT: adrp x8, localvar
57-
; CHECK-GI-NEXT: ldr w0, [x8, :lo12:localvar]
58-
; CHECK-GI-NEXT: ret
5940
entry:
6041
%0 = load i32, ptr @localvar, align 4
6142
ret i32 %0
@@ -67,12 +48,6 @@ define dso_local i32 @getLocalCommon() {
6748
; CHECK-NEXT: adrp x8, localcommon
6849
; CHECK-NEXT: ldr w0, [x8, :lo12:localcommon]
6950
; CHECK-NEXT: ret
70-
;
71-
; CHECK-GI-LABEL: getLocalCommon:
72-
; CHECK-GI: // %bb.0: // %entry
73-
; CHECK-GI-NEXT: adrp x8, localcommon
74-
; CHECK-GI-NEXT: ldr w0, [x8, :lo12:localcommon]
75-
; CHECK-GI-NEXT: ret
7651
entry:
7752
%0 = load i32, ptr @localcommon, align 4
7853
ret i32 %0
@@ -85,13 +60,6 @@ define dso_local i32 @getExtVar() {
8560
; CHECK-NEXT: ldr x8, [x8, :lo12:__imp_extvar]
8661
; CHECK-NEXT: ldr w0, [x8]
8762
; CHECK-NEXT: ret
88-
;
89-
; CHECK-GI-LABEL: getExtVar:
90-
; CHECK-GI: // %bb.0: // %entry
91-
; CHECK-GI-NEXT: adrp x8, __imp_extvar
92-
; CHECK-GI-NEXT: ldr x8, [x8, :lo12:__imp_extvar]
93-
; CHECK-GI-NEXT: ldr w0, [x8]
94-
; CHECK-GI-NEXT: ret
9563
entry:
9664
%0 = load i32, ptr @extvar, align 4
9765
ret i32 %0
@@ -101,10 +69,6 @@ define dso_local void @callFunc() {
10169
; CHECK-LABEL: callFunc:
10270
; CHECK: // %bb.0: // %entry
10371
; CHECK-NEXT: b otherFunc
104-
;
105-
; CHECK-GI-LABEL: callFunc:
106-
; CHECK-GI: // %bb.0: // %entry
107-
; CHECK-GI-NEXT: b otherFunc
10872
entry:
10973
tail call void @otherFunc()
11074
ret void
@@ -113,41 +77,41 @@ entry:
11377
declare dso_local void @otherFunc()
11478

11579
define dso_local void @sspFunc() #0 {
116-
; CHECK-LABEL: sspFunc:
117-
; CHECK: .seh_proc sspFunc
118-
; CHECK-NEXT: // %bb.0: // %entry
119-
; CHECK-NEXT: sub sp, sp, #32
120-
; CHECK-NEXT: .seh_stackalloc 32
121-
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
122-
; CHECK-NEXT: .seh_save_reg x30, 16
123-
; CHECK-NEXT: .seh_endprologue
124-
; CHECK-NEXT: adrp x8, .refptr.__stack_chk_guard
125-
; CHECK-NEXT: add x0, sp, #7
126-
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
127-
; CHECK-NEXT: ldr x8, [x8]
128-
; CHECK-NEXT: sub x8, sp, x8
129-
; CHECK-NEXT: str x8, [sp, #8]
130-
; CHECK-NEXT: bl ptrUser
131-
; CHECK-NEXT: adrp x8, .refptr.__stack_chk_guard
132-
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
133-
; CHECK-NEXT: ldr x9, [sp, #8]
134-
; CHECK-NEXT: ldr x8, [x8]
135-
; CHECK-NEXT: sub x8, sp, x8
136-
; CHECK-NEXT: cmp x8, x9
137-
; CHECK-NEXT: b.ne .LBB6_2
138-
; CHECK-NEXT: // %bb.1: // %entry
139-
; CHECK-NEXT: .seh_startepilogue
140-
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
141-
; CHECK-NEXT: .seh_save_reg x30, 16
142-
; CHECK-NEXT: add sp, sp, #32
143-
; CHECK-NEXT: .seh_stackalloc 32
144-
; CHECK-NEXT: .seh_endepilogue
145-
; CHECK-NEXT: ret
146-
; CHECK-NEXT: .LBB6_2: // %entry
147-
; CHECK-NEXT: bl __stack_chk_fail
148-
; CHECK-NEXT: brk #0x1
149-
; CHECK-NEXT: .seh_endfunclet
150-
; CHECK-NEXT: .seh_endproc
80+
; CHECK-SD-LABEL: sspFunc:
81+
; CHECK-SD: .seh_proc sspFunc
82+
; CHECK-SD-NEXT: // %bb.0: // %entry
83+
; CHECK-SD-NEXT: sub sp, sp, #32
84+
; CHECK-SD-NEXT: .seh_stackalloc 32
85+
; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
86+
; CHECK-SD-NEXT: .seh_save_reg x30, 16
87+
; CHECK-SD-NEXT: .seh_endprologue
88+
; CHECK-SD-NEXT: adrp x8, .refptr.__stack_chk_guard
89+
; CHECK-SD-NEXT: add x0, sp, #7
90+
; CHECK-SD-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
91+
; CHECK-SD-NEXT: ldr x8, [x8]
92+
; CHECK-SD-NEXT: sub x8, sp, x8
93+
; CHECK-SD-NEXT: str x8, [sp, #8]
94+
; CHECK-SD-NEXT: bl ptrUser
95+
; CHECK-SD-NEXT: adrp x8, .refptr.__stack_chk_guard
96+
; CHECK-SD-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
97+
; CHECK-SD-NEXT: ldr x9, [sp, #8]
98+
; CHECK-SD-NEXT: ldr x8, [x8]
99+
; CHECK-SD-NEXT: sub x8, sp, x8
100+
; CHECK-SD-NEXT: cmp x8, x9
101+
; CHECK-SD-NEXT: b.ne .LBB6_2
102+
; CHECK-SD-NEXT: // %bb.1: // %entry
103+
; CHECK-SD-NEXT: .seh_startepilogue
104+
; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
105+
; CHECK-SD-NEXT: .seh_save_reg x30, 16
106+
; CHECK-SD-NEXT: add sp, sp, #32
107+
; CHECK-SD-NEXT: .seh_stackalloc 32
108+
; CHECK-SD-NEXT: .seh_endepilogue
109+
; CHECK-SD-NEXT: ret
110+
; CHECK-SD-NEXT: .LBB6_2: // %entry
111+
; CHECK-SD-NEXT: bl __stack_chk_fail
112+
; CHECK-SD-NEXT: brk #0x1
113+
; CHECK-SD-NEXT: .seh_endfunclet
114+
; CHECK-SD-NEXT: .seh_endproc
151115
;
152116
; CHECK-GI-LABEL: sspFunc:
153117
; CHECK-GI: .seh_proc sspFunc
@@ -205,5 +169,3 @@ attributes #0 = { sspstrong }
205169
; CHECK: .refptr.var:
206170
; CHECK: .xword var
207171

208-
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
209-
; CHECK-SD: {{.*}}

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