[RISCV][Peephole] Checking regclass compatibility in VMV

Author: BeMg

llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp

@@ -565,6 +565,11 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
   if (MI.getOperand(1).getReg() != RISCV::NoRegister)
     return false;
 
+  const TargetRegisterClass *RC1 = MRI->getRegClass(MI.getOperand(0).getReg());
+  const TargetRegisterClass *RC2 = MRI->getRegClass(MI.getOperand(2).getReg());
+  if (!RC1->hasSubClassEq(RC2))
+    return false;
+
   // If the input was a pseudo with a policy operand, we can give it a tail
   // agnostic policy if MI's undef tail subsumes the input's.
   MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
@@ -608,6 +613,11 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
   if (!MRI->hasOneUse(MI.getOperand(2).getReg()))
     return false;
 
+  const TargetRegisterClass *RC1 = MRI->getRegClass(MI.getOperand(0).getReg());
+  const TargetRegisterClass *RC2 = MRI->getRegClass(MI.getOperand(2).getReg());
+  if (!RC1->hasSubClassEq(RC2))
+    return false;
+
   MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
   if (!Src || Src->hasUnmodeledSideEffects() ||
       Src->getParent() != MI.getParent() || Src->getNumDefs() != 1 ||

llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmv-with-different-class.mir

@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
 # RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
-# RUN: | FileCheck %s
+# RUN: -verify-machineinstrs | FileCheck %s
 
 --- |
   source_filename = "reduced.ll"
@@ -107,9 +107,10 @@ body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: main
     ; CHECK: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: [[PseudoVMV_V_V_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_V_MF2 $noreg, [[PseudoVMV_V_I_MF2_]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
-    ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_V_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
     ; CHECK-NEXT: early-clobber %6:vrnov0 = PseudoVWMACC_VV_MF2_MASK [[PseudoVMV_V_I_M1_]], killed [[PseudoVXOR_VV_MF2_MASK]], [[PseudoVMV_V_I_MF2_]], [[COPY1]], 0, 5 /* e32 */, 0 /* tu, mu */