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| 1 | +//===-- AMDGPUMLSchedStrategy.cpp - ML-focused Scheduler Strategy ---------===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | +// |
| 9 | +/// \file |
| 10 | +/// ML-focused scheduling strategy for AMDGPU. |
| 11 | +// |
| 12 | +//===----------------------------------------------------------------------===// |
| 13 | + |
| 14 | +#include "AMDGPUMLSchedStrategy.h" |
| 15 | + |
| 16 | +using namespace llvm; |
| 17 | + |
| 18 | +AMDGPUMLSchedStrategy::AMDGPUMLSchedStrategy(const MachineSchedContext *C) |
| 19 | + : GCNSchedStrategy(C) { |
| 20 | + SchedStages.push_back(GCNSchedStageID::ILPInitialSchedule); |
| 21 | + SchedStages.push_back(GCNSchedStageID::PreRARematerialize); |
| 22 | + // Use more accurate GCN pressure trackers. |
| 23 | + UseGCNTrackers = true; |
| 24 | +} |
| 25 | + |
| 26 | +bool AMDGPUMLSchedStrategy::tryCandidate(SchedCandidate &Cand, |
| 27 | + SchedCandidate &TryCand, |
| 28 | + SchedBoundary *Zone) const { |
| 29 | + // Initialize the candidate if needed. |
| 30 | + if (!Cand.isValid()) { |
| 31 | + TryCand.Reason = FirstValid; |
| 32 | + return true; |
| 33 | + } |
| 34 | + |
| 35 | + // Bias PhysReg Defs and copies to their uses and defined respectively. |
| 36 | + if (tryGreater(biasPhysReg(TryCand.SU, TryCand.AtTop), |
| 37 | + biasPhysReg(Cand.SU, Cand.AtTop), TryCand, Cand, PhysReg)) |
| 38 | + return TryCand.Reason != NoCand; |
| 39 | + |
| 40 | + // Avoid exceeding the target's limit. |
| 41 | + if (DAG->isTrackingPressure() && |
| 42 | + tryPressure(TryCand.RPDelta.Excess, Cand.RPDelta.Excess, TryCand, Cand, |
| 43 | + RegExcess, TRI, DAG->MF)) |
| 44 | + return TryCand.Reason != NoCand; |
| 45 | + |
| 46 | + // We only compare a subset of features when comparing nodes between |
| 47 | + // Top and Bottom boundary. Some properties are simply incomparable, in many |
| 48 | + // other instances we should only override the other boundary if something |
| 49 | + // is a clear good pick on one boundary. Skip heuristics that are more |
| 50 | + // "tie-breaking" in nature. |
| 51 | + bool SameBoundary = Zone != nullptr; |
| 52 | + if (SameBoundary) { |
| 53 | + // For loops that are acyclic path limited, aggressively schedule for |
| 54 | + // latency. Within an single cycle, whenever CurrMOps > 0, allow normal |
| 55 | + // heuristics to take precedence. |
| 56 | + if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() && |
| 57 | + tryLatency(TryCand, Cand, *Zone)) |
| 58 | + return TryCand.Reason != NoCand; |
| 59 | + |
| 60 | + // Prioritize instructions that read unbuffered resources by stall cycles. |
| 61 | + if (tryLess(Zone->getLatencyStallCycles(TryCand.SU), |
| 62 | + Zone->getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall)) |
| 63 | + return TryCand.Reason != NoCand; |
| 64 | + } |
| 65 | + |
| 66 | + // Keep clustered nodes together to encourage downstream peephole |
| 67 | + // optimizations which may reduce resource requirements. |
| 68 | + // |
| 69 | + // This is a best effort to set things up for a post-RA pass. Optimizations |
| 70 | + // like generating loads of multiple registers should ideally be done within |
| 71 | + // the scheduler pass by combining the loads during DAG postprocessing. |
| 72 | + unsigned CandZoneCluster = Cand.AtTop ? TopClusterID : BotClusterID; |
| 73 | + unsigned TryCandZoneCluster = TryCand.AtTop ? TopClusterID : BotClusterID; |
| 74 | + bool CandIsClusterSucc = |
| 75 | + isTheSameCluster(CandZoneCluster, Cand.SU->ParentClusterIdx); |
| 76 | + bool TryCandIsClusterSucc = |
| 77 | + isTheSameCluster(TryCandZoneCluster, TryCand.SU->ParentClusterIdx); |
| 78 | + |
| 79 | + if (tryGreater(TryCandIsClusterSucc, CandIsClusterSucc, TryCand, Cand, |
| 80 | + Cluster)) |
| 81 | + return TryCand.Reason != NoCand; |
| 82 | + |
| 83 | + if (SameBoundary) { |
| 84 | + // Weak edges are for clustering and other constraints. |
| 85 | + if (tryLess(getWeakLeft(TryCand.SU, TryCand.AtTop), |
| 86 | + getWeakLeft(Cand.SU, Cand.AtTop), TryCand, Cand, Weak)) |
| 87 | + return TryCand.Reason != NoCand; |
| 88 | + } |
| 89 | + |
| 90 | + // Avoid increasing the max pressure of the entire region. |
| 91 | + if (DAG->isTrackingPressure() && |
| 92 | + tryPressure(TryCand.RPDelta.CurrentMax, Cand.RPDelta.CurrentMax, TryCand, |
| 93 | + Cand, RegMax, TRI, DAG->MF)) |
| 94 | + return TryCand.Reason != NoCand; |
| 95 | + |
| 96 | + if (SameBoundary) { |
| 97 | + // Avoid critical resource consumption and balance the schedule. |
| 98 | + TryCand.initResourceDelta(DAG, SchedModel); |
| 99 | + if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources, |
| 100 | + TryCand, Cand, ResourceReduce)) |
| 101 | + return TryCand.Reason != NoCand; |
| 102 | + if (tryGreater(TryCand.ResDelta.DemandedResources, |
| 103 | + Cand.ResDelta.DemandedResources, TryCand, Cand, |
| 104 | + ResourceDemand)) |
| 105 | + return TryCand.Reason != NoCand; |
| 106 | + |
| 107 | + // Avoid serializing long latency dependence chains. |
| 108 | + // For acyclic path limited loops, latency was already checked above. |
| 109 | + if (!RegionPolicy.DisableLatencyHeuristic && TryCand.Policy.ReduceLatency && |
| 110 | + !Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, *Zone)) |
| 111 | + return TryCand.Reason != NoCand; |
| 112 | + |
| 113 | + // Fall through to original instruction order. |
| 114 | + if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) || |
| 115 | + (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) { |
| 116 | + TryCand.Reason = NodeOrder; |
| 117 | + return true; |
| 118 | + } |
| 119 | + } |
| 120 | + |
| 121 | + return false; |
| 122 | +} |
| 123 | + |
| 124 | +AMDGPUMLPostSchedStrategy::AMDGPUMLPostSchedStrategy( |
| 125 | + const MachineSchedContext *C) |
| 126 | + : PostGenericScheduler(C) {} |
| 127 | + |
| 128 | +bool AMDGPUMLPostSchedStrategy::tryCandidate(SchedCandidate &Cand, |
| 129 | + SchedCandidate &TryCand) { |
| 130 | + // Initialize the candidate if needed. |
| 131 | + if (!Cand.isValid()) { |
| 132 | + TryCand.Reason = FirstValid; |
| 133 | + return true; |
| 134 | + } |
| 135 | + |
| 136 | + // Prioritize instructions that read unbuffered resources by stall cycles. |
| 137 | + if (tryLess(Top.getLatencyStallCycles(TryCand.SU), |
| 138 | + Top.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall)) |
| 139 | + return TryCand.Reason != NoCand; |
| 140 | + |
| 141 | + // Keep clustered nodes together. |
| 142 | + unsigned CandZoneCluster = Cand.AtTop ? TopClusterID : BotClusterID; |
| 143 | + unsigned TryCandZoneCluster = TryCand.AtTop ? TopClusterID : BotClusterID; |
| 144 | + bool CandIsClusterSucc = |
| 145 | + isTheSameCluster(CandZoneCluster, Cand.SU->ParentClusterIdx); |
| 146 | + bool TryCandIsClusterSucc = |
| 147 | + isTheSameCluster(TryCandZoneCluster, TryCand.SU->ParentClusterIdx); |
| 148 | + |
| 149 | + if (tryGreater(TryCandIsClusterSucc, CandIsClusterSucc, TryCand, Cand, |
| 150 | + Cluster)) |
| 151 | + return TryCand.Reason != NoCand; |
| 152 | + // Avoid critical resource consumption and balance the schedule. |
| 153 | + if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources, |
| 154 | + TryCand, Cand, ResourceReduce)) |
| 155 | + return TryCand.Reason != NoCand; |
| 156 | + if (tryGreater(TryCand.ResDelta.DemandedResources, |
| 157 | + Cand.ResDelta.DemandedResources, TryCand, Cand, |
| 158 | + ResourceDemand)) |
| 159 | + return TryCand.Reason != NoCand; |
| 160 | + |
| 161 | + // We only compare a subset of features when comparing nodes between |
| 162 | + // Top and Bottom boundary. |
| 163 | + if (Cand.AtTop == TryCand.AtTop) { |
| 164 | + // Avoid serializing long latency dependence chains. |
| 165 | + if (Cand.Policy.ReduceLatency && |
| 166 | + tryLatency(TryCand, Cand, Cand.AtTop ? Top : Bot)) |
| 167 | + return TryCand.Reason != NoCand; |
| 168 | + } |
| 169 | + |
| 170 | + // Fall through to original instruction order. |
| 171 | + if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { |
| 172 | + TryCand.Reason = NodeOrder; |
| 173 | + return true; |
| 174 | + } |
| 175 | + |
| 176 | + return false; |
| 177 | +} |
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