The following changes made to addressed the comments like

  a)Refactored the code for proper indent with clang format.
  b)Updated SelectAddrRegImm9 to fall back to already isel exist pattern for ADD.
  c)Used UTC (utils/update_llc_test_checks.py) to generate the FileCheck CHECKS
  d)Updated the llvm-mc testcase accordingly.

Author: ukalappa-mips

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -1525,9 +1525,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
         Operands, ErrorInfo, 0, (1 << 8) - 8,
         "immediate must be a multiple of 8 bytes in the range");
   case Match_InvalidUImm9:
-    return generateImmOutOfRangeError(
-        Operands, ErrorInfo, 0, (1 << 9) - 1,
-        "immediate offset must be in the range[0-511]");
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 9) - 1,
+                                      "immediate offset must be in the range");
   case Match_InvalidBareSImm9Lsb0:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2,

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

@@ -790,7 +790,8 @@ static constexpr DecoderListEntry DecoderList32[]{
     {DecoderTableXmipscmov32,
      {RISCV::FeatureVendorXMIPSCMov},
      "MIPS mips.ccmov"},
-    {DecoderTableXmipscbop32, {RISCV::FeatureVendorXMIPSCBOP},
+    {DecoderTableXmipscbop32,
+     {RISCV::FeatureVendorXMIPSCBOP},
      "MIPS mips.pref"},
     {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
     // Standard Extensions

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -2945,22 +2945,6 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
       Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
       return true;
     }
-
-    // Handle with 12 bit offset with sign bit off with ADDI.
-    // For Immediate Range [0, 2047]
-    else if (Addr.getOpcode() == ISD::ADD &&
-             isa<ConstantSDNode>(Addr.getOperand(1))) {
-      assert(!isUInt<9>(CVal) && "uimm9 not already handled?");
-
-      if (isUInt<11>(CVal)) {
-        Base = SDValue(CurDAG->getMachineNode(
-                           RISCV::ADDI, DL, VT, Addr.getOperand(0),
-                           CurDAG->getSignedTargetConstant(CVal, DL, VT)),
-                       0);
-        Offset = CurDAG->getTargetConstant(0, DL, VT);
-        return true;
-      }
-    }
   }
 
   Base = Addr;

llvm/test/CodeGen/RISCV/xmips-cbop.ll

@@ -1,30 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32XMIPSPREFETCH
 ; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64XMIPSPREFETCH
 
 define void @prefetch_read(ptr noundef %ptr) nounwind {
 ; RV32XMIPSPREFETCH-LABEL: prefetch_read:
-; RV32XMIPSPREFETCH:    mips.pref       8, 1(a0)
+; RV32XMIPSPREFETCH:       # %bb.0: # %entry
+; RV32XMIPSPREFETCH-NEXT:    mips.pref 8, 1(a0)
+; RV32XMIPSPREFETCH-NEXT:    ret
 ;
 ; RV64XMIPSPREFETCH-LABEL: prefetch_read:
-; RV64XMIPSPREFETCH:    mips.pref       8, 1(a0)
+; RV64XMIPSPREFETCH:       # %bb.0: # %entry
+; RV64XMIPSPREFETCH-NEXT:    mips.pref 8, 1(a0)
+; RV64XMIPSPREFETCH-NEXT:    ret
 entry:
   %arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 1
   tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 0, i32 0, i32 1)
   ret void
-  ret void
 }
- 
+
 define void @prefetch_write(ptr noundef %ptr) nounwind  {
 ; RV32XMIPSPREFETCH-LABEL: prefetch_write:
-; RV32XMIPSPREFETCH:         addi    a0, a0, 512  
-; RV32XMIPSPREFETCH-NEXT:    mips.pref       9, 0(a0)
+; RV32XMIPSPREFETCH:       # %bb.0:
+; RV32XMIPSPREFETCH-NEXT:    addi a0, a0, 512
+; RV32XMIPSPREFETCH-NEXT:    mips.pref 9, 0(a0)
+; RV32XMIPSPREFETCH-NEXT:    ret
 ;
 ; RV64XMIPSPREFETCH-LABEL: prefetch_write:
-; RV64XMIPSPREFETCH:         addi    a0, a0, 512 
-; RV64XMIPSPREFETCH-NEXT:    mips.pref       9, 0(a0)
-entry:
+; RV64XMIPSPREFETCH:       # %bb.0:
+; RV64XMIPSPREFETCH-NEXT:    addi a0, a0, 512
+; RV64XMIPSPREFETCH-NEXT:    mips.pref 9, 0(a0)
+; RV64XMIPSPREFETCH-NEXT:    ret
   %arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 512
   tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 1, i32 0, i32 1)
   ret void

llvm/test/MC/RISCV/xmips-invalid.s

@@ -1,8 +1,8 @@
 # RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE
-# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipsbcop < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+Xmipscbop < %s 2>&1 | FileCheck %s
 
 mips.pref   8, 512(a0)
-# CHECK: error: invalid operand for instruction
+# CHECK: error: immediate offset must be in the range [0, 511]
 
 mips.pref	8
 # CHECK: error: too few operands for instruction

llvm/test/MC/RISCV/xmips-valid.s

@@ -8,13 +8,13 @@
 # CHECK-ENC:  encoding: [0x0b,0x04,0xf5,0x1f]
 mips.pref	8, 511(a0)
 
-# CHECK-DIS: mips.perf 0x8, 0x1ff(a0)
+# CHECK-DIS: mips.pref  0x8, 0x1ff(a0)
 
 # CHECK-INST: mips.pref 9, 0(a0)
 # CHECK-ENC:  encoding: [0x8b,0x04,0x05,0x00]
 mips.pref	9, 0(a0)
 
-# CHECK-DIS: mips.perf 0x9, 0x0(a0)
+# CHECK-DIS: mips.pref  0x9, 0x0(a0)
 
 # CHECK-INST: mips.ccmov	s0, s1, s2, s3
 # CHECK-ENC:  encoding: [0x0b,0x34,0x99,0x9e]