Simplify & rename variables

Author: HolyMolyCowMan

llvm/lib/Target/AArch64/AArch64Combine.td

@@ -333,10 +333,10 @@ def combine_mul_cmlt : GICombineRule<
 >;
 
 def combine_build_unmerge : GICombineRule<
-  (defs root:$root, register_vector_matchinfo:$unmergedValues, register_vector_matchinfo:$undefinedValues),
+  (defs root:$root, register_vector_matchinfo:$unmergeSrc, register_vector_matchinfo:$undefinedValues),
   (match (wip_match_opcode G_BUILD_VECTOR):$root,
-         [{ return matchCombineBuildUnmerge(*${root}, MRI, ${unmergedValues}, ${undefinedValues}); }]),
-  (apply [{ applyCombineBuildUnmerge(*${root}, MRI, B, ${unmergedValues}, ${undefinedValues}); }])
+         [{ return matchCombineBuildUnmerge(*${root}, MRI, ${unmergeSrc}, ${undefinedValues}); }]),
+  (apply [{ applyCombineBuildUnmerge(*${root}, MRI, B, ${unmergeSrc}, ${undefinedValues}); }])
 >;
 
 // Post-legalization combines which should happen at all optimization levels.

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

@@ -42,7 +42,6 @@
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/CodeGenTypes/MachineValueType.h"
 #include "llvm/Support/Debug.h"
-#include <cassert>
 #include <set>
 
 #define GET_GICOMBINER_DEPS
@@ -139,12 +138,12 @@ bool isZeroExtended(Register R, MachineRegisterInfo &MRI) {
 }
 
 bool matchCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
-                              SmallVectorImpl<Register> &unmergedValues,
+                              SmallVectorImpl<Register> &unmergeSrc,
                               SmallVectorImpl<Register> &undefinedValues) {
   assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
 
   undefinedValues.clear();
-  unmergedValues.clear();
+  unmergeSrc.clear();
 
   std::set<int> knownRegs;
 
@@ -153,7 +152,7 @@ bool matchCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
 
     if (!Def) {
       undefinedValues.clear();
-      unmergedValues.clear();
+      unmergeSrc.clear();
       return false;
     }
 
@@ -166,27 +165,30 @@ bool matchCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
       undefinedValues.push_back(Use.getReg());
       break;
     case TargetOpcode::G_UNMERGE_VALUES:
-      if (Def->getNumDefs() > 2 ||
+      // We only want to match G_UNMERGE_VALUES <2 x Ty>
+      // s16 is troublesome as <2 x s16> is generally not legal
+      if (Def->getNumDefs() != 2 ||
           MRI.getType(Use.getReg()) == LLT::scalar(16)) {
         undefinedValues.clear();
-        unmergedValues.clear();
+        unmergeSrc.clear();
         return false;
       }
-      if (knownRegs.find(Def->getOperand(2).getReg().id()) == knownRegs.end()) {
-        knownRegs.insert(Def->getOperand(2).getReg().id());
-        unmergedValues.push_back(Def->getOperand(2).getReg());
-      } 
-      else
-        continue;
 
+      // Only track unique sources for the G_UNMERGE_VALUES
+      if (knownRegs.find(Def->getOperand(2).getReg().id()) != knownRegs.end())
+        continue; 
+
+      knownRegs.insert(Def->getOperand(2).getReg().id());
+      unmergeSrc.push_back(Def->getOperand(2).getReg());
+      
       break;
     }
   }
 
-  if (!(undefinedValues.size() == 2 && unmergedValues.size() == 1) &&
-      !(undefinedValues.size() == 0 && unmergedValues.size() == 2)) {
+  // Only want to match patterns that pad two values with two undefined values
+  if (!(undefinedValues.size() == 2 && unmergeSrc.size() == 1)) {
     undefinedValues.clear();
-    unmergedValues.clear();
+    unmergeSrc.clear();
     return false;
   }
 
@@ -195,23 +197,19 @@ bool matchCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
 
 void applyCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
                               MachineIRBuilder &B,
-                              SmallVectorImpl<Register> &unmergedValues,
+                              SmallVectorImpl<Register> &unmergeSrc,
                               SmallVectorImpl<Register> &undefinedValues) {
+  assert(unmergeSrc.size() == 1 && "Expected there to be one G_UNMERGE_VALUES");
   B.setInstrAndDebugLoc(MI);
 
-  if (unmergedValues.size() == 1) {
     auto llt = LLT::fixed_vector(
         undefinedValues.size(),
-        LLT::scalar(MRI.getType(unmergedValues[0]).getScalarSizeInBits()));
+        LLT::scalar(MRI.getType(unmergeSrc[0]).getScalarSizeInBits()));
+
     Register DefVec = MRI.createGenericVirtualRegister(llt);
 
     B.buildBuildVector(DefVec, undefinedValues);
-    B.buildConcatVectors(MI.getOperand(0), {unmergedValues[0], DefVec});
-  } else {
-    return;
-    B.buildConcatVectors(MI.getOperand(0),
-                         {unmergedValues[0], unmergedValues[1]});
-  }
+    B.buildConcatVectors(MI.getOperand(0), {unmergeSrc[0], DefVec});
 
   MI.eraseFromParent();
 }