Skip to content

Commit bd64f31

Browse files
topperctopperc
committed
Recommit "[ARM] Change FastISel Address from a struct to a class. NFC"
With clang-format this time. Original message: This allows us to use Register in the interface, but store an unsigned internally in a union.
1 parent bc02802 commit bd64f31

File tree

1 file changed

+95
-59
lines changed

1 file changed

+95
-59
lines changed

‎llvm/lib/Target/ARM/ARMFastISel.cpp‎

Lines changed: 95 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -83,24 +83,51 @@ using namespace llvm;
8383
namespace {
8484

8585
// All possible address modes, plus some.
86-
struct Address {
87-
enum {
88-
RegBase,
89-
FrameIndexBase
90-
} BaseType = RegBase;
91-
92-
union {
93-
unsigned Reg;
94-
int FI;
95-
} Base;
96-
97-
int Offset = 0;
98-
99-
// Innocuous defaults for our address.
100-
Address() {
101-
Base.Reg = 0;
102-
}
103-
};
86+
class Address {
87+
public:
88+
using BaseKind = enum { RegBase, FrameIndexBase };
89+
90+
private:
91+
BaseKind Kind = RegBase;
92+
union {
93+
unsigned Reg;
94+
int FI;
95+
} Base;
96+
97+
int Offset = 0;
98+
99+
public:
100+
// Innocuous defaults for our address.
101+
Address() { Base.Reg = 0; }
102+
103+
void setKind(BaseKind K) { Kind = K; }
104+
BaseKind getKind() const { return Kind; }
105+
bool isRegBase() const { return Kind == RegBase; }
106+
bool isFIBase() const { return Kind == FrameIndexBase; }
107+
108+
void setReg(Register Reg) {
109+
assert(isRegBase() && "Invalid base register access!");
110+
Base.Reg = Reg.id();
111+
}
112+
113+
Register getReg() const {
114+
assert(isRegBase() && "Invalid base register access!");
115+
return Base.Reg;
116+
}
117+
118+
void setFI(int FI) {
119+
assert(isFIBase() && "Invalid base frame index access!");
120+
Base.FI = FI;
121+
}
122+
123+
int getFI() const {
124+
assert(isFIBase() && "Invalid base frame index access!");
125+
return Base.FI;
126+
}
127+
128+
void setOffset(int O) { Offset = O; }
129+
int getOffset() { return Offset; }
130+
};
104131

105132
class ARMFastISel final : public FastISel {
106133
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
@@ -738,7 +765,7 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
738765
break;
739766
case Instruction::GetElementPtr: {
740767
Address SavedAddr = Addr;
741-
int TmpOffset = Addr.Offset;
768+
int TmpOffset = Addr.getOffset();
742769

743770
// Iterate through the GEP folding the constants into offsets where
744771
// we can.
@@ -774,7 +801,7 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
774801
}
775802

776803
// Try to grab the base operand now.
777-
Addr.Offset = TmpOffset;
804+
Addr.setOffset(TmpOffset);
778805
if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
779806

780807
// We failed, restore everything and try the other options.
@@ -788,17 +815,18 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
788815
DenseMap<const AllocaInst*, int>::iterator SI =
789816
FuncInfo.StaticAllocaMap.find(AI);
790817
if (SI != FuncInfo.StaticAllocaMap.end()) {
791-
Addr.BaseType = Address::FrameIndexBase;
792-
Addr.Base.FI = SI->second;
818+
Addr.setKind(Address::FrameIndexBase);
819+
Addr.setFI(SI->second);
793820
return true;
794821
}
795822
break;
796823
}
797824
}
798825

799826
// Try to get this in a register if nothing else has worked.
800-
if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
801-
return Addr.Base.Reg != 0;
827+
if (!Addr.getReg())
828+
Addr.setReg(getRegForValue(Obj));
829+
return Addr.getReg();
802830
}
803831

804832
void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
@@ -811,45 +839,45 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
811839
case MVT::i32:
812840
if (!useAM3) {
813841
// Integer loads/stores handle 12-bit offsets.
814-
needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
842+
needsLowering = ((Addr.getOffset() & 0xfff) != Addr.getOffset());
815843
// Handle negative offsets.
816844
if (needsLowering && isThumb2)
817-
needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
818-
Addr.Offset > -256);
845+
needsLowering = !(Subtarget->hasV6T2Ops() && Addr.getOffset() < 0 &&
846+
Addr.getOffset() > -256);
819847
} else {
820848
// ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
821-
needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
849+
needsLowering = (Addr.getOffset() > 255 || Addr.getOffset() < -255);
822850
}
823851
break;
824852
case MVT::f32:
825853
case MVT::f64:
826854
// Floating point operands handle 8-bit offsets.
827-
needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
855+
needsLowering = ((Addr.getOffset() & 0xff) != Addr.getOffset());
828856
break;
829857
}
830858

831859
// If this is a stack pointer and the offset needs to be simplified then
832860
// put the alloca address into a register, set the base type back to
833861
// register and continue. This should almost never happen.
834-
if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
862+
if (needsLowering && Addr.isFIBase()) {
835863
const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
836864
: &ARM::GPRRegClass;
837865
Register ResultReg = createResultReg(RC);
838866
unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
839-
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
840-
TII.get(Opc), ResultReg)
841-
.addFrameIndex(Addr.Base.FI)
842-
.addImm(0));
843-
Addr.Base.Reg = ResultReg;
844-
Addr.BaseType = Address::RegBase;
867+
AddOptionalDefs(
868+
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
869+
.addFrameIndex(Addr.getFI())
870+
.addImm(0));
871+
Addr.setKind(Address::RegBase);
872+
Addr.setReg(ResultReg);
845873
}
846874

847875
// Since the offset is too large for the load/store instruction
848876
// get the reg+offset into a register.
849877
if (needsLowering) {
850-
Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
851-
Addr.Offset, MVT::i32);
852-
Addr.Offset = 0;
878+
Addr.setReg(fastEmit_ri_(MVT::i32, ISD::ADD, Addr.getReg(),
879+
Addr.getOffset(), MVT::i32));
880+
Addr.setOffset(0);
853881
}
854882
}
855883

@@ -860,12 +888,12 @@ void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
860888
// addrmode5 output depends on the selection dag addressing dividing the
861889
// offset by 4 that it then later multiplies. Do this here as well.
862890
if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
863-
Addr.Offset /= 4;
891+
Addr.setOffset(Addr.getOffset() / 4);
864892

865893
// Frame base works a bit differently. Handle it separately.
866-
if (Addr.BaseType == Address::FrameIndexBase) {
867-
int FI = Addr.Base.FI;
868-
int Offset = Addr.Offset;
894+
if (Addr.isFIBase()) {
895+
int FI = Addr.getFI();
896+
int Offset = Addr.getOffset();
869897
MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
870898
MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags,
871899
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
@@ -875,25 +903,27 @@ void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
875903
// ARM halfword load/stores and signed byte loads need an additional
876904
// operand.
877905
if (useAM3) {
878-
int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
906+
int Imm = (Addr.getOffset() < 0) ? (0x100 | -Addr.getOffset())
907+
: Addr.getOffset();
879908
MIB.addReg(0);
880909
MIB.addImm(Imm);
881910
} else {
882-
MIB.addImm(Addr.Offset);
911+
MIB.addImm(Addr.getOffset());
883912
}
884913
MIB.addMemOperand(MMO);
885914
} else {
886915
// Now add the rest of the operands.
887-
MIB.addReg(Addr.Base.Reg);
916+
MIB.addReg(Addr.getReg());
888917

889918
// ARM halfword load/stores and signed byte loads need an additional
890919
// operand.
891920
if (useAM3) {
892-
int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
921+
int Imm = (Addr.getOffset() < 0) ? (0x100 | -Addr.getOffset())
922+
: Addr.getOffset();
893923
MIB.addReg(0);
894924
MIB.addImm(Imm);
895925
} else {
896-
MIB.addImm(Addr.Offset);
926+
MIB.addImm(Addr.getOffset());
897927
}
898928
}
899929
AddOptionalDefs(MIB);
@@ -912,7 +942,8 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
912942
case MVT::i1:
913943
case MVT::i8:
914944
if (isThumb2) {
915-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
945+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
946+
Subtarget->hasV6T2Ops())
916947
Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
917948
else
918949
Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
@@ -932,7 +963,8 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
932963
return false;
933964

934965
if (isThumb2) {
935-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
966+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
967+
Subtarget->hasV6T2Ops())
936968
Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
937969
else
938970
Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
@@ -948,7 +980,8 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
948980
return false;
949981

950982
if (isThumb2) {
951-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
983+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
984+
Subtarget->hasV6T2Ops())
952985
Opc = ARM::t2LDRi8;
953986
else
954987
Opc = ARM::t2LDRi12;
@@ -1061,7 +1094,8 @@ bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
10611094
}
10621095
case MVT::i8:
10631096
if (isThumb2) {
1064-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1097+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
1098+
Subtarget->hasV6T2Ops())
10651099
StrOpc = ARM::t2STRBi8;
10661100
else
10671101
StrOpc = ARM::t2STRBi12;
@@ -1075,7 +1109,8 @@ bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
10751109
return false;
10761110

10771111
if (isThumb2) {
1078-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1112+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
1113+
Subtarget->hasV6T2Ops())
10791114
StrOpc = ARM::t2STRHi8;
10801115
else
10811116
StrOpc = ARM::t2STRHi12;
@@ -1090,7 +1125,8 @@ bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
10901125
return false;
10911126

10921127
if (isThumb2) {
1093-
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1128+
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 &&
1129+
Subtarget->hasV6T2Ops())
10941130
StrOpc = ARM::t2STRi8;
10951131
else
10961132
StrOpc = ARM::t2STRi12;
@@ -2031,9 +2067,9 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
20312067
continue;
20322068

20332069
Address Addr;
2034-
Addr.BaseType = Address::RegBase;
2035-
Addr.Base.Reg = ARM::SP;
2036-
Addr.Offset = VA.getLocMemOffset();
2070+
Addr.setKind(Address::RegBase);
2071+
Addr.setReg(ARM::SP);
2072+
Addr.setOffset(VA.getLocMemOffset());
20372073

20382074
bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
20392075
assert(EmitRet && "Could not emit a store for argument!");
@@ -2506,8 +2542,8 @@ bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
25062542

25072543
unsigned Size = VT.getSizeInBits()/8;
25082544
Len -= Size;
2509-
Dest.Offset += Size;
2510-
Src.Offset += Size;
2545+
Dest.setOffset(Dest.getOffset() + Size);
2546+
Src.setOffset(Src.getOffset() + Size);
25112547
}
25122548

25132549
return true;

0 commit comments

Comments
 (0)