Change function name to shouldInsertTrailingSeqCstFenceForAtomicStore

Update comment as well.

Change-Id: If5929f66da99cf9750c9c5f73aed295c2a5cf734

Author: UsmanNadeem

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -2235,6 +2235,14 @@ class LLVM_ABI TargetLoweringBase {
     return false;
   }
 
+  /// Whether AtomicExpandPass should automatically insert a seq_cst trailing
+  /// fence without reducing the ordering for this atomic store. Defaults to
+  /// false.
+  virtual bool
+  shouldInsertTrailingSeqCstFenceForAtomicStore(const Instruction *I) const {
+    return false;
+  }
+
   // The memory ordering that AtomicExpandPass should assign to a atomic
   // instruction that it has lowered by adding fences. This can be used
   // to "fold" one of the fences into the atomic instruction.
@@ -2243,12 +2251,6 @@ class LLVM_ABI TargetLoweringBase {
     return AtomicOrdering::Monotonic;
   }
 
-  /// Whether AtomicExpandPass should automatically insert a trailing fence
-  /// without reducing the ordering for this atomic. Defaults to false.
-  virtual bool storeNeedsSeqCstTrailingFence(const Instruction *I) const {
-    return false;
-  }
-
   /// Perform a load-linked operation on Addr, returning a "Value *" with the
   /// corresponding pointee type. This may entail some non-trivial operations to
   /// truncate or reconstruct types that will be illegal in the backend. See

llvm/lib/CodeGen/AtomicExpandPass.cpp

@@ -345,7 +345,7 @@ bool AtomicExpandImpl::processAtomicInstr(Instruction *I) {
     if (FenceOrdering != AtomicOrdering::Monotonic) {
       MadeChange |= bracketInstWithFences(I, FenceOrdering);
     }
-  } else if (TLI->storeNeedsSeqCstTrailingFence(I) &&
+  } else if (TLI->shouldInsertTrailingSeqCstFenceForAtomicStore(I) &&
              !(CASI && TLI->shouldExpandAtomicCmpXchgInIR(CASI) ==
                            TargetLoweringBase::AtomicExpansionKind::LLSC)) {
     // CmpXchg LLSC is handled in expandAtomicCmpXchg().
@@ -1503,7 +1503,8 @@ bool AtomicExpandImpl::expandAtomicCmpXchg(AtomicCmpXchgInst *CI) {
   // Make sure later instructions don't get reordered with a fence if
   // necessary.
   Builder.SetInsertPoint(SuccessBB);
-  if (ShouldInsertFencesForAtomic || TLI->storeNeedsSeqCstTrailingFence(CI))
+  if (ShouldInsertFencesForAtomic ||
+      TLI->shouldInsertTrailingSeqCstFenceForAtomicStore(CI))
     TLI->emitTrailingFence(Builder, CI, SuccessOrder);
   Builder.CreateBr(ExitBB);
 

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -29446,7 +29446,7 @@ bool AArch64TargetLowering::shouldInsertFencesForAtomic(
   return false;
 }
 
-bool AArch64TargetLowering::storeNeedsSeqCstTrailingFence(
+bool AArch64TargetLowering::shouldInsertTrailingSeqCstFenceForAtomicStore(
     const Instruction *I) const {
   // Store-Release instructions only provide seq_cst guarantees when paired with
   // Load-Acquire instructions. MSVC CRT does not use these instructions to

llvm/lib/Target/AArch64/AArch64ISelLowering.h

@@ -349,7 +349,8 @@ class AArch64TargetLowering : public TargetLowering {
   bool isOpSuitableForLSE128(const Instruction *I) const;
   bool isOpSuitableForRCPC3(const Instruction *I) const;
   bool shouldInsertFencesForAtomic(const Instruction *I) const override;
-  bool storeNeedsSeqCstTrailingFence(const Instruction *I) const override;
+  bool shouldInsertTrailingSeqCstFenceForAtomicStore(
+      const Instruction *I) const override;
 
   TargetLoweringBase::AtomicExpansionKind
   shouldExpandAtomicLoadInIR(LoadInst *LI) const override;