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Add the EOR instruction in AArch64InstrInfo::expandPostRAPseudo
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6 files changed

+30
-47
lines changed

6 files changed

+30
-47
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 1 addition & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -29239,25 +29239,7 @@ void AArch64TargetLowering::ReplaceNodeResults(
2923929239
bool AArch64TargetLowering::useLoadStackGuardNode(const Module &M) const {
2924029240
if (Subtarget->isTargetAndroid() || Subtarget->isTargetFuchsia())
2924129241
return TargetLowering::useLoadStackGuardNode(M);
29242-
return !Subtarget->getTargetTriple().isOSMSVCRT() ||
29243-
Subtarget->isTargetMachO() ||
29244-
getTargetMachine().Options.EnableGlobalISel;
29245-
}
29246-
29247-
bool AArch64TargetLowering::useStackGuardXorFP() const {
29248-
// Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
29249-
return Subtarget->getTargetTriple().isOSMSVCRT() &&
29250-
!Subtarget->isTargetMachO() &&
29251-
!getTargetMachine().Options.EnableGlobalISel;
29252-
}
29253-
29254-
SDValue AArch64TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG,
29255-
SDValue Val,
29256-
const SDLoc &DL) const {
29257-
return DAG.getNode(ISD::XOR, DL, Val.getValueType(), Val,
29258-
DAG.getCopyFromReg(DAG.getEntryNode(), DL,
29259-
getStackPointerRegisterToSaveRestore(),
29260-
MVT::i64));
29242+
return true;
2926129243
}
2926229244

2926329245
unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -363,9 +363,6 @@ class AArch64TargetLowering : public TargetLowering {
363363
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
364364

365365
bool useLoadStackGuardNode(const Module &M) const override;
366-
bool useStackGuardXorFP() const override;
367-
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
368-
const SDLoc &DL) const override;
369366
TargetLoweringBase::LegalizeTypeAction
370367
getPreferredVectorAction(MVT VT) const override;
371368

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2496,6 +2496,14 @@ bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
24962496
.addGlobalAddress(GV, 0, LoFlags)
24972497
.addMemOperand(*MI.memoperands_begin());
24982498
}
2499+
if (Subtarget.getTargetTriple().isOSMSVCRT() &&
2500+
!Subtarget.getTargetLowering()
2501+
->getTargetMachine()
2502+
.Options.EnableGlobalISel) {
2503+
BuildMI(MBB, MI, DL, get(AArch64::EORWrr), Reg)
2504+
.addReg(Reg, RegState::Kill)
2505+
.addReg(AArch64::SP);
2506+
}
24992507
}
25002508

25012509
MBB.erase(MI);

‎llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ void AArch64SelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
3838
return;
3939
}
4040

41-
// SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
41+
SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
4242

4343
#ifndef NDEBUG
4444
// Some additional checks not yet implemented by verifyTargetNode.

‎llvm/test/CodeGen/AArch64/mingw-refptr.ll‎

Lines changed: 12 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22
; RUN: llc < %s -mtriple=aarch64-w64-mingw32 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3-
; RUN: llc < %s -mtriple=aarch64-w64-mingw32 -global-isel | FileCheck %s --check-prefixes=CHECK-GI
3+
; RUN: llc < %s -mtriple=aarch64-w64-mingw32 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
@var = external local_unnamed_addr global i32, align 4
66
@dsolocalvar = external dso_local local_unnamed_addr global i32, align 4
@@ -118,31 +118,25 @@ define dso_local void @sspFunc() #0 {
118118
; CHECK-NEXT: // %bb.0: // %entry
119119
; CHECK-NEXT: sub sp, sp, #32
120120
; CHECK-NEXT: .seh_stackalloc 32
121-
; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill
122-
; CHECK-NEXT: .seh_save_reg x19, 16
123-
; CHECK-NEXT: str x30, [sp, #24] // 8-byte Spill
124-
; CHECK-NEXT: .seh_save_reg x30, 24
121+
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
122+
; CHECK-NEXT: .seh_save_reg x30, 16
125123
; CHECK-NEXT: .seh_endprologue
126-
; CHECK-NEXT: adrp x19, .refptr.__stack_chk_guard
127-
; CHECK-NEXT: mov x9, sp
124+
; CHECK-NEXT: adrp x8, .refptr.__stack_chk_guard
128125
; CHECK-NEXT: add x0, sp, #7
129-
; CHECK-NEXT: ldr x19, [x19, :lo12:.refptr.__stack_chk_guard]
130-
; CHECK-NEXT: ldr x8, [x19]
131-
; CHECK-NEXT: eor x8, x8, x9
126+
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
127+
; CHECK-NEXT: ldr x8, [x8]
132128
; CHECK-NEXT: str x8, [sp, #8]
133129
; CHECK-NEXT: bl ptrUser
130+
; CHECK-NEXT: adrp x8, .refptr.__stack_chk_guard
131+
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
134132
; CHECK-NEXT: ldr x9, [sp, #8]
135-
; CHECK-NEXT: mov x8, sp
136-
; CHECK-NEXT: ldr x10, [x19]
137-
; CHECK-NEXT: eor x8, x9, x8
138-
; CHECK-NEXT: cmp x10, x8
133+
; CHECK-NEXT: ldr x8, [x8]
134+
; CHECK-NEXT: cmp x8, x9
139135
; CHECK-NEXT: b.ne .LBB6_2
140136
; CHECK-NEXT: // %bb.1: // %entry
141137
; CHECK-NEXT: .seh_startepilogue
142-
; CHECK-NEXT: ldr x30, [sp, #24] // 8-byte Reload
143-
; CHECK-NEXT: .seh_save_reg x30, 24
144-
; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload
145-
; CHECK-NEXT: .seh_save_reg x19, 16
138+
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
139+
; CHECK-NEXT: .seh_save_reg x30, 16
146140
; CHECK-NEXT: add sp, sp, #32
147141
; CHECK-NEXT: .seh_stackalloc 32
148142
; CHECK-NEXT: .seh_endepilogue

‎llvm/test/CodeGen/AArch64/stack-protector-target.ll‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -29,16 +29,18 @@ declare void @_Z7CapturePi(ptr)
2929
; FUCHSIA-AARCH64-COMMON: ldr [[D:.*]], [sp,
3030
; FUCHSIA-AARCH64-COMMON: cmp [[C]], [[D]]
3131

32-
; WINDOWS-AARCH64: adrp x19, __security_cookie
33-
; WINDOWS-AARCH64: ldr x8, [x19, :lo12:__security_cookie]
32+
; WINDOWS-AARCH64: adrp x8, __security_cookie
33+
; WINDOWS-AARCH64: ldr x8, [x8, :lo12:__security_cookie]
34+
; WINDOWS-AARCH64: eor x8, x8, sp
3435
; WINDOWS-AARCH64: str x8, [sp, #8]
3536
; WINDOWS-AARCH64: bl _Z7CapturePi
36-
; WINDOWS-AARCH64: ldr x8, [sp, #8]
37+
; WINDOWS-AARCH64: ldr x0, [sp, #8]
3738
; WINDOWS-AARCH64: bl __security_check_cookie
3839

39-
; WINDOWS-ARM64EC: adrp x19, __security_cookie
40-
; WINDOWS-ARM64EC: ldr x8, [x19, :lo12:__security_cookie]
40+
; WINDOWS-ARM64EC: adrp x8, __security_cookie
41+
; WINDOWS-ARM64EC: ldr x8, [x8, :lo12:__security_cookie]
42+
; WINDOWS-ARM64EC: eor x8, x8, sp
4143
; WINDOWS-ARM64EC: str x8, [sp, #8]
4244
; WINDOWS-ARM64EC: bl "#_Z7CapturePi"
43-
; WINDOWS-ARM64EC: ldr x8, [sp, #8]
45+
; WINDOWS-ARM64EC: ldr x0, [sp, #8]
4446
; WINDOWS-ARM64EC: bl "#__security_check_cookie_arm64ec"

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