For copy from physical reg, check the dst reg type is i1.

Author: jwanggit86

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

@@ -139,7 +139,7 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
     }
 
     // Allow copy from physical register other than SCC to s1.
-    if (SrcReg.isPhysical() && SrcReg != AMDGPU::SCC)
+    if (SrcReg.isPhysical() && MRI->getType(DstReg) == LLT::scalar(1))
       return true;
 
     if (!isVCC(SrcReg, *MRI)) {

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-sgpr-to-s1-wave32.mir

@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=instruction-select -o - %s | FileCheck -check-prefix=WAVE32 %s
 
 ---
 name: copy_sgpr_to_s1_vcc
@@ -72,67 +72,3 @@ body: |
     %1:vgpr(s32) = G_SELECT %0:vgpr(s1), %2:vgpr, %3:vgpr
     S_ENDPGM 0, implicit %1:vgpr(s32)
 ...
-
----
-name: copy_scc_to_s1_vcc
-legalized: true
-regBankSelected: true
-
-body: |
-  bb.0:
-    ; WAVE32-LABEL: name: copy_scc_to_s1_vcc
-    ; WAVE32:      [[COPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY $scc
-    ; WAVE32-NEXT: [[VMOV1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    ; WAVE32-NEXT: [[VMOV2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE32-NEXT: [[VCND:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[VMOV2]], 0, [[VMOV1]], [[COPY]], implicit $exec
-    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[VCND]]
-    ;
-    %0:vcc(s1) = COPY $scc
-    %2:vgpr(s32) = G_CONSTANT i32 1
-    %3:vgpr(s32) = G_CONSTANT i32 0
-    %1:vgpr(s32) = G_SELECT %0:vcc(s1), %2:vgpr, %3:vgpr
-    S_ENDPGM 0, implicit %1:vgpr(s32)
-...
-
----
-name: copy_scc_to_s1_sreg_32_xm0_xexec
-legalized: true
-regBankSelected: true
-
-body: |
-  bb.0:
-    ; WAVE32-LABEL: name: copy_scc_to_s1_sreg_32_xm0_xexec
-    ; WAVE32:      [[COPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY $scc
-    ; WAVE32-NEXT: [[VMOV1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    ; WAVE32-NEXT: [[VMOV2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE32-NEXT: [[VCND:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[VMOV2]], 0, [[VMOV1]], [[COPY]], implicit $exec
-    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[VCND]]
-    ;
-    %0:sreg_32_xm0_xexec(s1) = COPY $scc
-    %2:vgpr(s32) = G_CONSTANT i32 1
-    %3:vgpr(s32) = G_CONSTANT i32 0
-    %1:vgpr(s32) = G_SELECT %0:sreg_32_xm0_xexec(s1), %2:vgpr, %3:vgpr
-    S_ENDPGM 0, implicit %1:vgpr(s32)
-...
-
----
-name: copy_scc_to_s1_vgpr
-legalized: true
-regBankSelected: true
-
-body: |
-  bb.0:
-    ; WAVE32-LABEL: name: copy_scc_to_s1_vgpr
-    ; WAVE32:      [[COPY:%[0-9]+]]:vgpr_32 = COPY $scc
-    ; WAVE32-NEXT: [[VMOV1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    ; WAVE32-NEXT: [[VMOV2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY]]
-    ; WAVE32-NEXT: [[VCND:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[VMOV2]], 0, [[VMOV1]], [[COPY2]], implicit $exec
-    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[VCND]]
-    ;
-    %0:vgpr(s1) = COPY $scc
-    %2:vgpr(s32) = G_CONSTANT i32 1
-    %3:vgpr(s32) = G_CONSTANT i32 0
-    %1:vgpr(s32) = G_SELECT %0:vgpr(s1), %2:vgpr, %3:vgpr
-    S_ENDPGM 0, implicit %1:vgpr(s32)
-...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-sgpr-to-s1-wave64.mir

@@ -72,67 +72,3 @@ body: |
     %1:vgpr(s32) = G_SELECT %0(s1), %2, %3
     S_ENDPGM 0, implicit %1(s32)
 ...
-
----
-name: copy_scc_to_s1_vcc
-legalized: true
-regBankSelected: true
-
-body: |
-  bb.0:
-    ; WAVE64-LABEL: name: copy_scc_to_s1_vcc
-    ; WAVE64:      [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $scc
-    ; WAVE64-NEXT: [[VMOV1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    ; WAVE64-NEXT: [[VMOV2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE64-NEXT: [[VCND:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[VMOV2]], 0, [[VMOV1]], [[COPY]], implicit $exec
-    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[VCND]]
-    ;
-    %0:vcc(s1) = COPY $scc
-    %2:vgpr(s32) = G_CONSTANT i32 1
-    %3:vgpr(s32) = G_CONSTANT i32 0
-    %1:vgpr(s32) = G_SELECT %0(s1), %2, %3
-    S_ENDPGM 0, implicit %1(s32)
-...
-
----
-name: copy_scc_to_s1_sreg_64_xexec
-legalized: true
-regBankSelected: true
-
-body: |
-  bb.0:
-    ; WAVE64-LABEL: name: copy_scc_to_s1_sreg_64_xexec
-    ; WAVE64:      [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $scc
-    ; WAVE64-NEXT: [[VMOV1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    ; WAVE64-NEXT: [[VMOV2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE64-NEXT: [[VCND:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[VMOV2]], 0, [[VMOV1]], [[COPY]], implicit $exec
-    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[VCND]]
-    ;
-    %0:sreg_64_xexec(s1) = COPY $scc
-    %2:vgpr(s32) = G_CONSTANT i32 1
-    %3:vgpr(s32) = G_CONSTANT i32 0
-    %1:vgpr(s32) = G_SELECT %0(s1), %2, %3
-    S_ENDPGM 0, implicit %1(s32)
-...
-
----
-name: copy_scc_to_s1_vgpr
-legalized: true
-regBankSelected: true
-
-body: |
-  bb.0:
-    ; WAVE64-LABEL: name: copy_scc_to_s1_vgpr
-    ; WAVE64:      [[COPY:%[0-9]+]]:vgpr_32 = COPY $scc
-    ; WAVE64-NEXT: [[VMOV1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    ; WAVE64-NEXT: [[VMOV2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]
-    ; WAVE64-NEXT: [[VCND:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[VMOV2]], 0, [[VMOV1]], [[COPY2]], implicit $exec
-    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[VCND]]
-    ;
-    %0:vgpr(s1) = COPY $scc
-    %2:vgpr(s32) = G_CONSTANT i32 1
-    %3:vgpr(s32) = G_CONSTANT i32 0
-    %1:vgpr(s32) = G_SELECT %0(s1), %2, %3
-    S_ENDPGM 0, implicit %1(s32)
-...