drop pure

Hardcode84 · Hardcode84 · commit c62230bd0e01 · 2025-08-07T20:01:54.000+02:00
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -203,7 +203,7 @@ def ROCDL_ReadfirstlaneOp : ROCDL_IntrOp<"readfirstlane", [], [0], [AllTypesMatc
   }];
 }
 
-def ROCDL_ReadlaneOp : ROCDL_IntrOp<"readlane", [], [0], [AllTypesMatch<["res", "src0"]>, Pure], 1>,
+def ROCDL_ReadlaneOp : ROCDL_IntrOp<"readlane", [], [0], [AllTypesMatch<["res", "src0"]>], 1>,
   Arguments<(ins LLVM_Type:$src0,
                  I32:$src1)> {
   let results = (outs LLVM_Type:$res);

Original file line number	Diff line number	Diff line change
`@@ -203,7 +203,7 @@ def ROCDL_ReadfirstlaneOp : ROCDL_IntrOp<"readfirstlane", [], [0], [AllTypesMatc`
`203`	`203`	`}];`
`204`	`204`	`}`
`205`	`205`
`206`		`-def ROCDL_ReadlaneOp : ROCDL_IntrOp<"readlane", [], [0], [AllTypesMatch<["res", "src0"]>, Pure], 1>,`
	`206`	`+def ROCDL_ReadlaneOp : ROCDL_IntrOp<"readlane", [], [0], [AllTypesMatch<["res", "src0"]>], 1>,`
`207`	`207`	`Arguments<(ins LLVM_Type:$src0,`
`208`	`208`	`I32:$src1)> {`
`209`	`209`	`let results = (outs LLVM_Type:$res);`