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moar55moar55
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Merge branch 'main' into support-x86-builtin-rotate
2 parents ac53a36 + 8459508 commit c816ccd

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2 files changed

+128
-10
lines changed

2 files changed

+128
-10
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp‎

Lines changed: 28 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -703,6 +703,23 @@ static SmallVector<VPUser *> collectUsersRecursively(VPValue *V) {
703703
return Users.takeVector();
704704
}
705705

706+
/// Scalarize a VPWidenPointerInductionRecipe by replacing it with a PtrAdd
707+
/// (IndStart, ScalarIVSteps (0, Step)). This is used when the recipe only
708+
/// generates scalar values.
709+
static VPValue *
710+
scalarizeVPWidenPointerInduction(VPWidenPointerInductionRecipe *PtrIV,
711+
VPlan &Plan, VPBuilder &Builder) {
712+
const InductionDescriptor &ID = PtrIV->getInductionDescriptor();
713+
VPValue *StartV = Plan.getConstantInt(ID.getStep()->getType(), 0);
714+
VPValue *StepV = PtrIV->getOperand(1);
715+
VPScalarIVStepsRecipe *Steps = createScalarIVSteps(
716+
Plan, InductionDescriptor::IK_IntInduction, Instruction::Add, nullptr,
717+
nullptr, StartV, StepV, PtrIV->getDebugLoc(), Builder);
718+
719+
return Builder.createPtrAdd(PtrIV->getStartValue(), Steps,
720+
PtrIV->getDebugLoc(), "next.gep");
721+
}
722+
706723
/// Legalize VPWidenPointerInductionRecipe, by replacing it with a PtrAdd
707724
/// (IndStart, ScalarIVSteps (0, Step)) if only its scalar values are used, as
708725
/// VPWidenPointerInductionRecipe will generate vectors only. If some users
@@ -755,16 +772,7 @@ static void legalizeAndOptimizeInductions(VPlan &Plan) {
755772
if (!PtrIV->onlyScalarsGenerated(Plan.hasScalableVF()))
756773
continue;
757774

758-
const InductionDescriptor &ID = PtrIV->getInductionDescriptor();
759-
VPValue *StartV = Plan.getConstantInt(ID.getStep()->getType(), 0);
760-
VPValue *StepV = PtrIV->getOperand(1);
761-
VPScalarIVStepsRecipe *Steps = createScalarIVSteps(
762-
Plan, InductionDescriptor::IK_IntInduction, Instruction::Add, nullptr,
763-
nullptr, StartV, StepV, PtrIV->getDebugLoc(), Builder);
764-
765-
VPValue *PtrAdd = Builder.createPtrAdd(PtrIV->getStartValue(), Steps,
766-
PtrIV->getDebugLoc(), "next.gep");
767-
775+
VPValue *PtrAdd = scalarizeVPWidenPointerInduction(PtrIV, Plan, Builder);
768776
PtrIV->replaceAllUsesWith(PtrAdd);
769777
continue;
770778
}
@@ -3575,6 +3583,16 @@ void VPlanTransforms::convertToConcreteRecipes(VPlan &Plan) {
35753583
}
35763584

35773585
if (auto *WidenIVR = dyn_cast<VPWidenPointerInductionRecipe>(&R)) {
3586+
// If the recipe only generates scalars, scalarize it instead of
3587+
// expanding it.
3588+
if (WidenIVR->onlyScalarsGenerated(Plan.hasScalableVF())) {
3589+
VPBuilder Builder(WidenIVR);
3590+
VPValue *PtrAdd =
3591+
scalarizeVPWidenPointerInduction(WidenIVR, Plan, Builder);
3592+
WidenIVR->replaceAllUsesWith(PtrAdd);
3593+
ToRemove.push_back(WidenIVR);
3594+
continue;
3595+
}
35783596
expandVPWidenPointerInduction(WidenIVR, TypeInfo);
35793597
ToRemove.push_back(WidenIVR);
35803598
continue;

‎llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll‎

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,4 +61,104 @@ exit:
6161
ret void
6262
}
6363

64+
define i1 @scalarize_ptr_induction(ptr %start, ptr %end, ptr noalias %dst, i1 %c) #1 {
65+
; CHECK-LABEL: define i1 @scalarize_ptr_induction(
66+
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]], ptr noalias [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR1:[0-9]+]] {
67+
; CHECK-NEXT: [[ENTRY:.*:]]
68+
; CHECK-NEXT: [[START5:%.*]] = ptrtoint ptr [[START]] to i64
69+
; CHECK-NEXT: [[END4:%.*]] = ptrtoint ptr [[END]] to i64
70+
; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
71+
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
72+
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END4]], -12
73+
; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START5]]
74+
; CHECK-NEXT: [[TMP2:%.*]] = udiv i64 [[TMP1]], 12
75+
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
76+
; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
77+
; CHECK: [[VECTOR_MEMCHECK]]:
78+
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 8
79+
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[END1]], -12
80+
; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[TMP6]], [[START2]]
81+
; CHECK-NEXT: [[TMP8:%.*]] = udiv i64 [[TMP7]], 12
82+
; CHECK-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 12
83+
; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 8
84+
; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP10]]
85+
; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP3]]
86+
; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[START]], [[SCEVGEP]]
87+
; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
88+
; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
89+
; CHECK: [[VECTOR_PH]]:
90+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[DST]], i64 0
91+
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 2 x ptr> poison, <vscale x 2 x i32> zeroinitializer
92+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT6:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[END]], i64 0
93+
; CHECK-NEXT: [[BROADCAST_SPLAT7:%.*]] = shufflevector <vscale x 2 x ptr> [[BROADCAST_SPLATINSERT6]], <vscale x 2 x ptr> poison, <vscale x 2 x i32> zeroinitializer
94+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
95+
; CHECK: [[VECTOR_BODY]]:
96+
; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[START]], %[[VECTOR_PH]] ], [ [[PTR_IND:%.*]], %[[VECTOR_BODY]] ]
97+
; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP3]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
98+
; CHECK-NEXT: [[TMP13:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()
99+
; CHECK-NEXT: [[TMP14:%.*]] = mul <vscale x 2 x i64> [[TMP13]], splat (i64 12)
100+
; CHECK-NEXT: [[VECTOR_GEP:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <vscale x 2 x i64> [[TMP14]]
101+
; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
102+
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, <vscale x 2 x ptr> [[VECTOR_GEP]], i64 4
103+
; CHECK-NEXT: [[TMP18:%.*]] = call <vscale x 2 x i32> @llvm.vp.gather.nxv2i32.nxv2p0(<vscale x 2 x ptr> align 4 [[TMP12]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP11]]), !alias.scope [[META3:![0-9]+]]
104+
; CHECK-NEXT: [[TMP19:%.*]] = zext <vscale x 2 x i32> [[TMP18]] to <vscale x 2 x i64>
105+
; CHECK-NEXT: [[TMP20:%.*]] = mul <vscale x 2 x i64> [[TMP19]], splat (i64 -7070675565921424023)
106+
; CHECK-NEXT: [[TMP21:%.*]] = add <vscale x 2 x i64> [[TMP20]], splat (i64 -4)
107+
; CHECK-NEXT: call void @llvm.vp.scatter.nxv2i64.nxv2p0(<vscale x 2 x i64> [[TMP21]], <vscale x 2 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP11]]), !alias.scope [[META6:![0-9]+]], !noalias [[META3]]
108+
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr nusw i8, <vscale x 2 x ptr> [[VECTOR_GEP]], i64 12
109+
; CHECK-NEXT: [[TMP17:%.*]] = icmp eq <vscale x 2 x ptr> [[TMP16]], [[BROADCAST_SPLAT7]]
110+
; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP11]] to i64
111+
; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP26]]
112+
; CHECK-NEXT: [[TMP27:%.*]] = mul i64 12, [[TMP26]]
113+
; CHECK-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i64 [[TMP27]]
114+
; CHECK-NEXT: [[TMP28:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
115+
; CHECK-NEXT: br i1 [[TMP28]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
116+
; CHECK: [[MIDDLE_BLOCK]]:
117+
; CHECK-NEXT: [[TMP29:%.*]] = sub i64 [[TMP26]], 1
118+
; CHECK-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
119+
; CHECK-NEXT: [[TMP23:%.*]] = mul nuw i64 [[TMP22]], 2
120+
; CHECK-NEXT: [[TMP24:%.*]] = mul i64 [[TMP23]], 0
121+
; CHECK-NEXT: [[TMP25:%.*]] = extractelement <vscale x 2 x i1> [[TMP17]], i64 [[TMP29]]
122+
; CHECK-NEXT: br label %[[EXIT:.*]]
123+
; CHECK: [[SCALAR_PH]]:
124+
; CHECK-NEXT: br label %[[LOOP:.*]]
125+
; CHECK: [[LOOP]]:
126+
; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[START]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]
127+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[PTR_IV]], i64 4
128+
; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4
129+
; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[L]] to i64
130+
; CHECK-NEXT: [[UNUSED:%.*]] = load i32, ptr [[PTR_IV]], align 4
131+
; CHECK-NEXT: [[MUL1:%.*]] = mul i64 [[EXT]], -7070675565921424023
132+
; CHECK-NEXT: [[MUL2:%.*]] = add i64 [[MUL1]], -4
133+
; CHECK-NEXT: store i64 [[MUL2]], ptr [[DST]], align 1
134+
; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr nusw i8, ptr [[PTR_IV]], i64 12
135+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]
136+
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 true, i1 false
137+
; CHECK-NEXT: br i1 [[OR_COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
138+
; CHECK: [[EXIT]]:
139+
; CHECK-NEXT: [[CMP_LCSSA:%.*]] = phi i1 [ [[CMP]], %[[LOOP]] ], [ [[TMP25]], %[[MIDDLE_BLOCK]] ]
140+
; CHECK-NEXT: ret i1 [[CMP_LCSSA]]
141+
;
142+
entry:
143+
br label %loop
144+
145+
loop:
146+
%ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop ]
147+
%gep = getelementptr i8, ptr %ptr.iv, i64 4
148+
%l = load i32, ptr %gep, align 4
149+
%ext = zext i32 %l to i64
150+
%unused = load i32, ptr %ptr.iv, align 4
151+
%mul1 = mul i64 %ext, -7070675565921424023
152+
%mul2 = add i64 %mul1, -4
153+
store i64 %mul2, ptr %dst, align 1
154+
%ptr.iv.next = getelementptr nusw i8, ptr %ptr.iv, i64 12
155+
%cmp = icmp eq ptr %ptr.iv.next, %end
156+
%or.cond = select i1 %cmp, i1 true, i1 false
157+
br i1 %or.cond, label %exit, label %loop
158+
159+
exit:
160+
ret i1 %cmp
161+
}
162+
64163
attributes #0 = { "target-features"="+v" }
164+
attributes #1 = { "target-cpu"="sifive-p670" }

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