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Populate check-lines before patching
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‎llvm/test/CodeGen/AMDGPU/integer-select-source-modifiers.ll

Lines changed: 170 additions & 0 deletions
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55
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
66

77
define i32 @fneg_select_i32(i32 %cond, i32 %a, i32 %b) {
8+
; GCN-LABEL: fneg_select_i32:
9+
; GCN: ; %bb.0:
10+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11+
; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
12+
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
13+
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
14+
; GCN-NEXT: s_setpc_b64 s[30:31]
15+
;
16+
; GFX11-LABEL: fneg_select_i32:
17+
; GFX11: ; %bb.0:
18+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
19+
; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
20+
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
21+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
22+
; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
23+
; GFX11-NEXT: s_setpc_b64 s[30:31]
824
%neg.a = xor i32 %a, u0x80000000
925
%cmp = icmp eq i32 %cond, zeroinitializer
1026
%select = select i1 %cmp, i32 %neg.a, i32 %b
1127
ret i32 %select
1228
}
1329

1430
define <2 x i32> @fneg_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
31+
; GCN-LABEL: fneg_select_v2i32:
32+
; GCN: ; %bb.0:
33+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
34+
; GCN-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
35+
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
36+
; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
37+
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
38+
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
39+
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
40+
; GCN-NEXT: s_setpc_b64 s[30:31]
41+
;
42+
; GFX11-LABEL: fneg_select_v2i32:
43+
; GFX11: ; %bb.0:
44+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
45+
; GFX11-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
46+
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
47+
; GFX11-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
48+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
49+
; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
50+
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
51+
; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo
52+
; GFX11-NEXT: s_setpc_b64 s[30:31]
1553
%neg.a = xor <2 x i32> %a, splat (i32 u0x80000000)
1654
%cmp = icmp eq <2 x i32> %cond, zeroinitializer
1755
%select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b
1856
ret <2 x i32> %select
1957
}
2058

2159
define i32 @fabs_select_i32(i32 %cond, i32 %a, i32 %b) {
60+
; GCN-LABEL: fabs_select_i32:
61+
; GCN: ; %bb.0:
62+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
63+
; GCN-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
64+
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
65+
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
66+
; GCN-NEXT: s_setpc_b64 s[30:31]
67+
;
68+
; GFX11-LABEL: fabs_select_i32:
69+
; GFX11: ; %bb.0:
70+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
71+
; GFX11-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
72+
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
73+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
74+
; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
75+
; GFX11-NEXT: s_setpc_b64 s[30:31]
2276
%neg.a = and i32 %a, u0x7fffffff
2377
%cmp = icmp eq i32 %cond, zeroinitializer
2478
%select = select i1 %cmp, i32 %neg.a, i32 %b
2579
ret i32 %select
2680
}
2781

2882
define <2 x i32> @fabs_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
83+
; GCN-LABEL: fabs_select_v2i32:
84+
; GCN: ; %bb.0:
85+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
86+
; GCN-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
87+
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
88+
; GCN-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
89+
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
90+
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
91+
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
92+
; GCN-NEXT: s_setpc_b64 s[30:31]
93+
;
94+
; GFX11-LABEL: fabs_select_v2i32:
95+
; GFX11: ; %bb.0:
96+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
97+
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
98+
; GFX11-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
99+
; GFX11-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
100+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
101+
; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
102+
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
103+
; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo
104+
; GFX11-NEXT: s_setpc_b64 s[30:31]
29105
%neg.a = and <2 x i32> %a, splat (i32 u0x7fffffff)
30106
%cmp = icmp eq <2 x i32> %cond, zeroinitializer
31107
%select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b
32108
ret <2 x i32> %select
33109
}
34110

35111
define i32 @fneg_fabs_select_i32(i32 %cond, i32 %a, i32 %b) {
112+
; GCN-LABEL: fneg_fabs_select_i32:
113+
; GCN: ; %bb.0:
114+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
115+
; GCN-NEXT: v_or_b32_e32 v1, 0x80000000, v1
116+
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
117+
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
118+
; GCN-NEXT: s_setpc_b64 s[30:31]
119+
;
120+
; GFX11-LABEL: fneg_fabs_select_i32:
121+
; GFX11: ; %bb.0:
122+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
123+
; GFX11-NEXT: v_or_b32_e32 v1, 0x80000000, v1
124+
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
125+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
126+
; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
127+
; GFX11-NEXT: s_setpc_b64 s[30:31]
36128
%neg.a = or i32 %a, u0x80000000
37129
%cmp = icmp eq i32 %cond, zeroinitializer
38130
%select = select i1 %cmp, i32 %neg.a, i32 %b
39131
ret i32 %select
40132
}
41133

42134
define <2 x i32> @fneg_fabs_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) {
135+
; GCN-LABEL: fneg_fabs_select_v2i32:
136+
; GCN: ; %bb.0:
137+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
138+
; GCN-NEXT: v_or_b32_e32 v2, 0x80000000, v2
139+
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
140+
; GCN-NEXT: v_or_b32_e32 v3, 0x80000000, v3
141+
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
142+
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
143+
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
144+
; GCN-NEXT: s_setpc_b64 s[30:31]
145+
;
146+
; GFX11-LABEL: fneg_fabs_select_v2i32:
147+
; GFX11: ; %bb.0:
148+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
149+
; GFX11-NEXT: v_or_b32_e32 v2, 0x80000000, v2
150+
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
151+
; GFX11-NEXT: v_or_b32_e32 v3, 0x80000000, v3
152+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
153+
; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
154+
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
155+
; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo
156+
; GFX11-NEXT: s_setpc_b64 s[30:31]
43157
%neg.a = or <2 x i32> %a, splat (i32 u0x80000000)
44158
%cmp = icmp eq <2 x i32> %cond, zeroinitializer
45159
%select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b
46160
ret <2 x i32> %select
47161
}
48162

49163
define i64 @fneg_select_i64(i64 %cond, i64 %a, i64 %b) {
164+
; GCN-LABEL: fneg_select_i64:
165+
; GCN: ; %bb.0:
166+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
167+
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
168+
; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
169+
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
170+
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
171+
; GCN-NEXT: s_setpc_b64 s[30:31]
172+
;
173+
; GFX11-LABEL: fneg_select_i64:
174+
; GFX11: ; %bb.0:
175+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
176+
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
177+
; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v3
178+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
179+
; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v2 :: v_dual_cndmask_b32 v1, v5, v1
180+
; GFX11-NEXT: s_setpc_b64 s[30:31]
50181
%neg.a = xor i64 %a, u0x8000000000000000
51182
%cmp = icmp eq i64 %cond, zeroinitializer
52183
%select = select i1 %cmp, i64 %neg.a, i64 %b
53184
ret i64 %select
54185
}
55186

56187
define i64 @fabs_select_i64(i64 %cond, i64 %a, i64 %b) {
188+
; GCN-LABEL: fabs_select_i64:
189+
; GCN: ; %bb.0:
190+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
191+
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
192+
; GCN-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
193+
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
194+
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
195+
; GCN-NEXT: s_setpc_b64 s[30:31]
196+
;
197+
; GFX11-LABEL: fabs_select_i64:
198+
; GFX11: ; %bb.0:
199+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
200+
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
201+
; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v2 :: v_dual_and_b32 v1, 0x7fffffff, v3
202+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
203+
; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
204+
; GFX11-NEXT: s_setpc_b64 s[30:31]
57205
%neg.a = and i64 %a, u0x7fffffffffffffff
58206
%cmp = icmp eq i64 %cond, zeroinitializer
59207
%select = select i1 %cmp, i64 %neg.a, i64 %b
60208
ret i64 %select
61209
}
62210

63211
define i64 @fneg_fabs_select_i64(i64 %cond, i64 %a, i64 %b) {
212+
; GCN-LABEL: fneg_fabs_select_i64:
213+
; GCN: ; %bb.0:
214+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
215+
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
216+
; GCN-NEXT: v_or_b32_e32 v3, 0x80000000, v3
217+
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
218+
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
219+
; GCN-NEXT: s_setpc_b64 s[30:31]
220+
;
221+
; GFX11-LABEL: fneg_fabs_select_i64:
222+
; GFX11: ; %bb.0:
223+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
224+
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
225+
; GFX11-NEXT: v_or_b32_e32 v1, 0x80000000, v3
226+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
227+
; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v2 :: v_dual_cndmask_b32 v1, v5, v1
228+
; GFX11-NEXT: s_setpc_b64 s[30:31]
64229
%neg.a = or i64 %a, u0x8000000000000000
65230
%cmp = icmp eq i64 %cond, zeroinitializer
66231
%select = select i1 %cmp, i64 %neg.a, i64 %b
67232
ret i64 %select
68233
}
234+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
235+
; GFX11-FAKE16: {{.*}}
236+
; GFX11-TRUE16: {{.*}}
237+
; GFX7: {{.*}}
238+
; GFX9: {{.*}}

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