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2 files changed

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2 files changed

+5
-3
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clang/lib/CodeGen/CGHLSLBuiltins.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -832,7 +832,8 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
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case Builtin::BI__builtin_hlsl_wave_active_bit_or: {
833833
Value *Op = EmitScalarExpr(E->getArg(0));
834834
assert(E->getArg(0)->getType()->hasUnsignedIntegerRepresentation() &&
835-
"Intrinsic WaveActiveBitOr operand must have a unsigned integer representation");
835+
"Intrinsic WaveActiveBitOr operand must have a unsigned integer "
836+
"representation");
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837838
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveBitOrIntrinsic();
838839
return EmitRuntimeCall(Intrinsic::getOrInsertDeclaration(

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2443,8 +2443,9 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits(
24432443
return Result;
24442444
}
24452445

2446-
bool SPIRVInstructionSelector::selectWaveReduceOr(
2447-
Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
2446+
bool SPIRVInstructionSelector::selectWaveReduceOr(Register ResVReg,
2447+
const SPIRVType *ResType,
2448+
MachineInstr &I) const {
24482449

24492450
assert(I.getNumOperands() == 3);
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assert(I.getOperand(2).isReg());

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