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Remove auto
1 parent 9c05865 commit d52729f

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4 files changed

+7
-7
lines changed

4 files changed

+7
-7
lines changed

clang/lib/CIR/CodeGen/CIRGenBuilder.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -398,7 +398,7 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy {
398398
mlir::Value addr, mlir::Type storageType,
399399
const CIRGenBitFieldInfo &info,
400400
bool isLvalueVolatile, bool useVolatile) {
401-
auto offset = useVolatile ? info.volatileOffset : info.offset;
401+
unsigned int offset = useVolatile ? info.volatileOffset : info.offset;
402402
return create<cir::GetBitfieldOp>(loc, resultType, addr, storageType,
403403
info.name, info.size, offset,
404404
info.isSigned, isLvalueVolatile);

clang/lib/CIR/CodeGen/CIRGenExpr.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -335,7 +335,7 @@ RValue CIRGenFunction::emitLoadOfBitfieldLValue(LValue lv, SourceLocation loc) {
335335

336336
assert(!cir::MissingFeatures::armComputeVolatileBitfields());
337337

338-
auto field = builder.createGetBitfield(getLoc(loc), resLTy, ptr.getPointer(),
338+
mlir::Value field = builder.createGetBitfield(getLoc(loc), resLTy, ptr.getPointer(),
339339
ptr.getElementType(), info,
340340
lv.isVolatile(), false);
341341
assert(!cir::MissingFeatures::opLoadEmitScalarRangeCheck() && "NYI");

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2346,7 +2346,7 @@ mlir::LogicalResult CIRToLLVMGetBitfieldOpLowering::matchAndRewrite(
23462346
}
23472347

23482348
mlir::Type resTy = getTypeConverter()->convertType(op.getType());
2349-
auto newOp = createIntCast(
2349+
mlir::Value newOp = createIntCast(
23502350
rewriter, val, mlir::cast<mlir::IntegerType>(resTy), info.getIsSigned());
23512351
rewriter.replaceOp(op, newOp);
23522352
return mlir::success();

clang/lib/CIR/Lowering/LoweringHelpers.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -159,26 +159,26 @@ mlir::Value getConst(mlir::OpBuilder &bld, mlir::Location loc, mlir::Type typ,
159159
mlir::Value createShL(mlir::OpBuilder &bld, mlir::Value lhs, unsigned rhs) {
160160
if (!rhs)
161161
return lhs;
162-
auto rhsVal = getConst(bld, lhs.getLoc(), lhs.getType(), rhs);
162+
mlir::Value rhsVal = getConst(bld, lhs.getLoc(), lhs.getType(), rhs);
163163
return bld.create<mlir::LLVM::ShlOp>(lhs.getLoc(), lhs, rhsVal);
164164
}
165165

166166
mlir::Value createAShR(mlir::OpBuilder &bld, mlir::Value lhs, unsigned rhs) {
167167
if (!rhs)
168168
return lhs;
169-
auto rhsVal = getConst(bld, lhs.getLoc(), lhs.getType(), rhs);
169+
mlir::Value rhsVal = getConst(bld, lhs.getLoc(), lhs.getType(), rhs);
170170
return bld.create<mlir::LLVM::AShrOp>(lhs.getLoc(), lhs, rhsVal);
171171
}
172172

173173
mlir::Value createAnd(mlir::OpBuilder &bld, mlir::Value lhs,
174174
const llvm::APInt &rhs) {
175-
auto rhsVal = getConstAPInt(bld, lhs.getLoc(), lhs.getType(), rhs);
175+
mlir::Value rhsVal = getConstAPInt(bld, lhs.getLoc(), lhs.getType(), rhs);
176176
return bld.create<mlir::LLVM::AndOp>(lhs.getLoc(), lhs, rhsVal);
177177
}
178178

179179
mlir::Value createLShR(mlir::OpBuilder &bld, mlir::Value lhs, unsigned rhs) {
180180
if (!rhs)
181181
return lhs;
182-
auto rhsVal = getConst(bld, lhs.getLoc(), lhs.getType(), rhs);
182+
mlir::Value rhsVal = getConst(bld, lhs.getLoc(), lhs.getType(), rhs);
183183
return bld.create<mlir::LLVM::LShrOp>(lhs.getLoc(), lhs, rhsVal);
184184
}

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