Incorporated changes for code review feedback.

Author: anoopkg6

clang/include/clang/Basic/TargetInfo.h

@@ -1114,12 +1114,11 @@ class TargetInfo : public TransferrableTargetInfo,
 
     std::string ConstraintStr;  // constraint: "=rm"
     std::string Name;           // Operand name: [foo] with no []'s.
-    unsigned FlagOutputCCUpperBound;
 
   public:
     ConstraintInfo(StringRef ConstraintStr, StringRef Name)
         : Flags(0), TiedOperand(-1), ConstraintStr(ConstraintStr.str()),
-          Name(Name.str()), FlagOutputCCUpperBound(0) {
+          Name(Name.str()) {
       ImmRange.Min = ImmRange.Max = 0;
       ImmRange.isConstrained = false;
     }
@@ -1191,13 +1190,13 @@ class TargetInfo : public TransferrableTargetInfo,
       // Don't copy Name or constraint string.
     }
 
-    // CC range can be set by target. SystemZ sets it to 4. It is 2 by default.
+    // CC range can be set by targets supporting flag output operand.
     void setFlagOutputCCUpperBound(unsigned CCBound) {
-      FlagOutputCCUpperBound = CCBound;
-    }
-    unsigned getFlagOutputCCUpperBound() const {
-      return FlagOutputCCUpperBound;
+      // Using ImmRange.Max to store CC upper bound. Interval [0, CCBound).
+      ImmRange.Max = CCBound;
+      ImmRange.isConstrained = true;
     }
+    unsigned getFlagOutputCCUpperBound() const { return ImmRange.Max; }
   };
 
   /// Validate register name used for global register variables.
@@ -1238,7 +1237,6 @@ class TargetInfo : public TransferrableTargetInfo,
                              std::string &/*SuggestedModifier*/) const {
     return true;
   }
-
   virtual bool
   validateAsmConstraint(const char *&Name,
                         TargetInfo::ConstraintInfo &info) const = 0;

clang/lib/Basic/Targets/SystemZ.cpp

@@ -103,6 +103,7 @@ bool SystemZTargetInfo::validateAsmConstraint(
     if (StringRef(Name) == "@cc") {
       Name += 2;
       Info.setAllowsRegister();
+      // SystemZ has 2-bits CC, and hence Interval [0, 4).
       Info.setFlagOutputCCUpperBound(4);
       return true;
     }

clang/lib/Basic/Targets/SystemZ.h

@@ -119,11 +119,13 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public TargetInfo {
                              TargetInfo::ConstraintInfo &info) const override;
 
   std::string convertConstraint(const char *&Constraint) const override {
-    if (llvm::StringRef(Constraint) == "@cc") {
-      Constraint += 2;
-      return std::string("{@cc}");
-    }
     switch (Constraint[0]) {
+    case '@': // Flag output operand.
+      if (llvm::StringRef(Constraint) == "@cc") {
+        Constraint += 2;
+        return std::string("{@cc}");
+      }
+      break;
     case 'p': // Keep 'p' constraint.
       return std::string("p");
     case 'Z':

clang/lib/CodeGen/CGStmt.cpp

@@ -2601,7 +2601,7 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
               const llvm::ArrayRef<LValue> ResultRegDests,
               const llvm::ArrayRef<QualType> ResultRegQualTys,
               const llvm::BitVector &ResultTypeRequiresCast,
-              const std::vector<unsigned> &ResultRegIsFlagReg) {
+              const std::vector<unsigned> &ResultFlagRegCCBound) {
   CGBuilderTy &Builder = CGF.Builder;
   CodeGenModule &CGM = CGF.CGM;
   llvm::LLVMContext &CTX = CGF.getLLVMContext();
@@ -2612,23 +2612,19 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
   // ResultRegDests can be also populated by addReturnRegisterOutputs() above,
   // in which case its size may grow.
   assert(ResultTypeRequiresCast.size() <= ResultRegDests.size());
-  assert(ResultRegIsFlagReg.size() <= ResultRegDests.size());
+  assert(ResultFlagRegCCBound.size() <= ResultRegDests.size());
 
   for (unsigned i = 0, e = RegResults.size(); i != e; ++i) {
     llvm::Value *Tmp = RegResults[i];
     llvm::Type *TruncTy = ResultTruncRegTypes[i];
 
-    if ((i < ResultRegIsFlagReg.size()) && ResultRegIsFlagReg[i]) {
+    if ((i < ResultFlagRegCCBound.size()) && ResultFlagRegCCBound[i]) {
       // Target must guarantee the Value `Tmp` here is lowered to a boolean
       // value.
-      // Lowering 'Tmp' as - 'icmp ult %Tmp , CCUpperBound'. On some targets
-      // CCUpperBound is not binary. CCUpperBound is 4 for SystemZ,
-      // interval [0, 4). With this range known, llvm.assume intrinsic guides
-      // optimizer to generate more optimized IR in most of the cases as
-      // observed for select_cc on SystemZ unit tests for flag output operands.
-      // For some cases for br_cc, generated IR was weird. e.g. switch table
-      // for simple simple comparison terms for br_cc.
-      unsigned CCUpperBound = ResultRegIsFlagReg[i];
+      // Lowering 'Tmp' as - 'icmp ult %Tmp , CCUpperBound'.
+      unsigned CCUpperBound = ResultFlagRegCCBound[i];
+      assert((CCUpperBound == 2 || CCUpperBound == 4) &&
+             "CC upper bound out of range!");
       llvm::Constant *CCUpperBoundConst =
           llvm::ConstantInt::get(Tmp->getType(), CCUpperBound);
       llvm::Value *IsBooleanValue =
@@ -2759,7 +2755,7 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
   std::vector<llvm::Type *> ArgElemTypes;
   std::vector<llvm::Value*> Args;
   llvm::BitVector ResultTypeRequiresCast;
-  std::vector<unsigned> ResultRegIsFlagReg;
+  std::vector<unsigned> ResultFlagRegCCBound;
 
   // Keep track of inout constraints.
   std::string InOutConstraints;
@@ -2817,7 +2813,7 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
       ResultRegQualTys.push_back(QTy);
       ResultRegDests.push_back(Dest);
 
-      ResultRegIsFlagReg.push_back(Info.getFlagOutputCCUpperBound());
+      ResultFlagRegCCBound.push_back(Info.getFlagOutputCCUpperBound());
 
       llvm::Type *Ty = ConvertTypeForMem(QTy);
       const bool RequiresCast = Info.allowsRegister() &&
@@ -3164,7 +3160,7 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
 
   EmitAsmStores(*this, S, RegResults, ResultRegTypes, ResultTruncRegTypes,
                 ResultRegDests, ResultRegQualTys, ResultTypeRequiresCast,
-                ResultRegIsFlagReg);
+                ResultFlagRegCCBound);
 
   // If this is an asm goto with outputs, repeat EmitAsmStores, but with a
   // different insertion point; one for each indirect destination and with
@@ -3175,7 +3171,7 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
       Builder.SetInsertPoint(Succ, --(Succ->end()));
       EmitAsmStores(*this, S, CBRRegResults[Succ], ResultRegTypes,
                     ResultTruncRegTypes, ResultRegDests, ResultRegQualTys,
-                    ResultTypeRequiresCast, ResultRegIsFlagReg);
+                    ResultTypeRequiresCast, ResultFlagRegCCBound);
     }
   }
 }

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

@@ -12117,13 +12117,12 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
         SDValue CondLHS = getValue(Cond);
         EVT VT = CondLHS.getValueType();
         SDLoc DL = getCurSDLoc();
-        SDValue Cond;
 
         SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
                                  DAG.getConstant(CommonBit, DL, VT));
-        Cond = DAG.getSetCC(DL, MVT::i1, Or,
-                            DAG.getConstant(BigValue | SmallValue, DL, VT),
-                            ISD::SETEQ);
+        SDValue Cond = DAG.getSetCC(
+            DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
+            ISD::SETEQ);
 
         // Update successor info.
         // Both Small and Big will jump to Small.BB, so we sum up the