Fix formatting of xorcombine - how did this regress?

Author: chrisjbris

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -13378,16 +13378,19 @@ SDValue SITargetLowering::performXorCombine(SDNode *N,
   // (v2i32 svelect cc, (xor x, K), (xor y, K)) This enables the xor to be
   // replaced with source modifiers when the select is lowered to CNDMASK.
   unsigned Opc = LHS.getOpcode();
-  if(((Opc == ISD::VSELECT && VT==MVT::v2i32) || (Opc == ISD::SELECT && VT==MVT::i64)) && CRHS && CRHS->getAPIntValue().isSignMask()) {
+  if (((Opc == ISD::VSELECT && VT == MVT::v2i32) ||
+       (Opc == ISD::SELECT && VT == MVT::i64)) &&
+      CRHS && CRHS->getAPIntValue().isSignMask()) {
     SDValue CC = LHS->getOperand(0);
     SDValue TRUE = LHS->getOperand(1);
     SDValue FALSE = LHS->getOperand(2);
     SDValue XTrue = DAG.getNode(ISD::XOR, SDLoc(N), VT, TRUE, RHS);
     SDValue XFalse = DAG.getNode(ISD::XOR, SDLoc(N), VT, FALSE, RHS);
-    SDValue XSelect = DAG.getNode(ISD::VSELECT, SDLoc(N), VT, CC, XTrue, XFalse);
+    SDValue XSelect =
+        DAG.getNode(ISD::VSELECT, SDLoc(N), VT, CC, XTrue, XFalse);
     return XSelect;
   }
-  
+
   // Make sure to apply the 64-bit constant splitting fold before trying to fold
   // fneg-like xors into 64-bit select.
   if (LHS.getOpcode() == ISD::SELECT && VT == MVT::i32) {