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1 parent 696bad8 commit d79e21cCopy full SHA for d79e21c
llvm/test/CodeGen/RISCV/zilsd-ldst-opt-postra.mir
@@ -200,8 +200,8 @@ body: |
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bb.0:
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liveins: $x10
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- ; PseudoLD_RV32_OPT with symbolic operand and non-consecutive registers (x11, x14)
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- ; Should decompose back to two LW instructions preserving symbolic references
+ ; PseudoLD_RV32_OPT with first destination register overlapping base register ($x11)
+ ; Should decompose back to two LW instructions when first reg overlaps base reg
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; CHECK-LABEL: name: overlapped_first_reg_base_reg
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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