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Restore range check for memory opcodes, too
1 parent 7f06770 commit d844547

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4 files changed

+11
-26
lines changed

4 files changed

+11
-26
lines changed

llvm/lib/Target/Mips/MipsISelLowering.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -247,14 +247,16 @@ class TargetRegisterClass;
247247
DOUBLE_SELECT_I64,
248248

249249
// Load/Store Left/Right nodes.
250-
LWL,
250+
FIRST_MEMORY_OPCODE,
251+
LWL = FIRST_MEMORY_OPCODE,
251252
LWR,
252253
SWL,
253254
SWR,
254255
LDL,
255256
LDR,
256257
SDL,
257-
SDR
258+
SDR,
259+
LAST_MEMORY_OPCODE = SDR,
258260
};
259261

260262
} // ene namespace MipsISD

llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp

Lines changed: 2 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -14,17 +14,6 @@ using namespace llvm;
1414
MipsSelectionDAGInfo::~MipsSelectionDAGInfo() = default;
1515

1616
bool MipsSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
17-
switch (static_cast<MipsISD::NodeType>(Opcode)) {
18-
default:
19-
return false;
20-
case MipsISD::LWL:
21-
case MipsISD::LWR:
22-
case MipsISD::SWL:
23-
case MipsISD::SWR:
24-
case MipsISD::LDL:
25-
case MipsISD::LDR:
26-
case MipsISD::SDL:
27-
case MipsISD::SDR:
28-
return true;
29-
}
17+
return Opcode >= MipsISD::FIRST_MEMORY_OPCODE &&
18+
Opcode <= MipsISD::LAST_MEMORY_OPCODE;
3019
}

llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -492,11 +492,13 @@ enum NodeType : unsigned {
492492
STRICT_VFROUND_NOEXCEPT_VL,
493493
LAST_STRICTFP_OPCODE = STRICT_VFROUND_NOEXCEPT_VL,
494494

495-
TH_LWD,
495+
FIRST_MEMORY_OPCODE,
496+
TH_LWD = FIRST_MEMORY_OPCODE,
496497
TH_LWUD,
497498
TH_LDD,
498499
TH_SWD,
499500
TH_SDD,
501+
LAST_MEMORY_OPCODE = TH_SDD,
500502
};
501503
// clang-format on
502504
} // namespace RISCVISD

llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,16 +14,8 @@ using namespace llvm;
1414
RISCVSelectionDAGInfo::~RISCVSelectionDAGInfo() = default;
1515

1616
bool RISCVSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
17-
switch (static_cast<RISCVISD::NodeType>(Opcode)) {
18-
default:
19-
return false;
20-
case RISCVISD::TH_LWD:
21-
case RISCVISD::TH_LWUD:
22-
case RISCVISD::TH_LDD:
23-
case RISCVISD::TH_SWD:
24-
case RISCVISD::TH_SDD:
25-
return true;
26-
}
17+
return Opcode >= RISCVISD::FIRST_MEMORY_OPCODE &&
18+
Opcode <= RISCVISD::LAST_MEMORY_OPCODE;
2719
}
2820

2921
bool RISCVSelectionDAGInfo::isTargetStrictFPOpcode(unsigned Opcode) const {

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