Skip to content

Commit ded86fd

Browse files
BeMgBeMg
committed
update testcase
1 parent 7ef1381 commit ded86fd

File tree

293 files changed

+17869
-21475
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

293 files changed

+17869
-21475
lines changed

‎llvm/test/CodeGen/RISCV/memcmp-optsize.ll‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1714,8 +1714,8 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind optsize {
17141714
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
17151715
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
17161716
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v10, (a1)
1717-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v12, v8, v10
1718-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v12
1717+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v10
1718+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
17191719
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
17201720
; CHECK-UNALIGNED-RV32-V-NEXT: ret
17211721
;
@@ -1724,8 +1724,8 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind optsize {
17241724
; CHECK-UNALIGNED-RV64-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
17251725
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
17261726
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v10, (a1)
1727-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v12, v8, v10
1728-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v12
1727+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v10
1728+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
17291729
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
17301730
; CHECK-UNALIGNED-RV64-V-NEXT: ret
17311731
entry:
@@ -1910,8 +1910,8 @@ define i32 @bcmp_size_32(ptr %s1, ptr %s2) nounwind optsize {
19101910
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m2, ta, ma
19111911
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
19121912
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v10, (a1)
1913-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v12, v8, v10
1914-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v12
1913+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v10
1914+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
19151915
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
19161916
; CHECK-UNALIGNED-RV32-V-NEXT: ret
19171917
;
@@ -1921,8 +1921,8 @@ define i32 @bcmp_size_32(ptr %s1, ptr %s2) nounwind optsize {
19211921
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m2, ta, ma
19221922
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
19231923
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v10, (a1)
1924-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v12, v8, v10
1925-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v12
1924+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v10
1925+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
19261926
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
19271927
; CHECK-UNALIGNED-RV64-V-NEXT: ret
19281928
entry:
@@ -2077,8 +2077,8 @@ define i32 @bcmp_size_63(ptr %s1, ptr %s2) nounwind optsize {
20772077
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
20782078
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
20792079
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v12, (a1)
2080-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v16, v8, v12
2081-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v16
2080+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v12
2081+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
20822082
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
20832083
; CHECK-UNALIGNED-RV32-V-NEXT: ret
20842084
;
@@ -2088,8 +2088,8 @@ define i32 @bcmp_size_63(ptr %s1, ptr %s2) nounwind optsize {
20882088
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
20892089
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
20902090
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v12, (a1)
2091-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v16, v8, v12
2092-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v16
2091+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v12
2092+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
20932093
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
20942094
; CHECK-UNALIGNED-RV64-V-NEXT: ret
20952095
entry:
@@ -2244,8 +2244,8 @@ define i32 @bcmp_size_64(ptr %s1, ptr %s2) nounwind optsize {
22442244
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
22452245
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
22462246
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v12, (a1)
2247-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v16, v8, v12
2248-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v16
2247+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v12
2248+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
22492249
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
22502250
; CHECK-UNALIGNED-RV32-V-NEXT: ret
22512251
;
@@ -2255,8 +2255,8 @@ define i32 @bcmp_size_64(ptr %s1, ptr %s2) nounwind optsize {
22552255
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
22562256
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
22572257
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v12, (a1)
2258-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v16, v8, v12
2259-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v16
2258+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v12
2259+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
22602260
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
22612261
; CHECK-UNALIGNED-RV64-V-NEXT: ret
22622262
entry:
@@ -2411,8 +2411,8 @@ define i32 @bcmp_size_127(ptr %s1, ptr %s2) nounwind optsize {
24112411
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
24122412
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
24132413
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v16, (a1)
2414-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v24, v8, v16
2415-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v24
2414+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v16
2415+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
24162416
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
24172417
; CHECK-UNALIGNED-RV32-V-NEXT: ret
24182418
;
@@ -2422,8 +2422,8 @@ define i32 @bcmp_size_127(ptr %s1, ptr %s2) nounwind optsize {
24222422
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
24232423
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
24242424
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v16, (a1)
2425-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v24, v8, v16
2426-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v24
2425+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v16
2426+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
24272427
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
24282428
; CHECK-UNALIGNED-RV64-V-NEXT: ret
24292429
entry:
@@ -2578,8 +2578,8 @@ define i32 @bcmp_size_128(ptr %s1, ptr %s2) nounwind optsize {
25782578
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
25792579
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
25802580
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v16, (a1)
2581-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v24, v8, v16
2582-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v24
2581+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v16
2582+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
25832583
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
25842584
; CHECK-UNALIGNED-RV32-V-NEXT: ret
25852585
;
@@ -2589,8 +2589,8 @@ define i32 @bcmp_size_128(ptr %s1, ptr %s2) nounwind optsize {
25892589
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
25902590
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
25912591
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v16, (a1)
2592-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v24, v8, v16
2593-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v24
2592+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v16
2593+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
25942594
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
25952595
; CHECK-UNALIGNED-RV64-V-NEXT: ret
25962596
entry:

‎llvm/test/CodeGen/RISCV/memcmp.ll‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1792,8 +1792,8 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind {
17921792
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
17931793
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
17941794
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v10, (a1)
1795-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v12, v8, v10
1796-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v12
1795+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v10
1796+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
17971797
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
17981798
; CHECK-UNALIGNED-RV32-V-NEXT: ret
17991799
;
@@ -1802,8 +1802,8 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind {
18021802
; CHECK-UNALIGNED-RV64-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
18031803
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
18041804
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v10, (a1)
1805-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v12, v8, v10
1806-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v12
1805+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v10
1806+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
18071807
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
18081808
; CHECK-UNALIGNED-RV64-V-NEXT: ret
18091809
entry:
@@ -2066,8 +2066,8 @@ define i32 @bcmp_size_32(ptr %s1, ptr %s2) nounwind {
20662066
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m2, ta, ma
20672067
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
20682068
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v10, (a1)
2069-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v12, v8, v10
2070-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v12
2069+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v10
2070+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
20712071
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
20722072
; CHECK-UNALIGNED-RV32-V-NEXT: ret
20732073
;
@@ -2077,8 +2077,8 @@ define i32 @bcmp_size_32(ptr %s1, ptr %s2) nounwind {
20772077
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m2, ta, ma
20782078
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
20792079
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v10, (a1)
2080-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v12, v8, v10
2081-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v12
2080+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v10
2081+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
20822082
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
20832083
; CHECK-UNALIGNED-RV64-V-NEXT: ret
20842084
entry:
@@ -2311,8 +2311,8 @@ define i32 @bcmp_size_63(ptr %s1, ptr %s2) nounwind {
23112311
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
23122312
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
23132313
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v12, (a1)
2314-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v16, v8, v12
2315-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v16
2314+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v12
2315+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
23162316
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
23172317
; CHECK-UNALIGNED-RV32-V-NEXT: ret
23182318
;
@@ -2322,8 +2322,8 @@ define i32 @bcmp_size_63(ptr %s1, ptr %s2) nounwind {
23222322
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
23232323
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
23242324
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v12, (a1)
2325-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v16, v8, v12
2326-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v16
2325+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v12
2326+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
23272327
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
23282328
; CHECK-UNALIGNED-RV64-V-NEXT: ret
23292329
entry:
@@ -2556,8 +2556,8 @@ define i32 @bcmp_size_64(ptr %s1, ptr %s2) nounwind {
25562556
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
25572557
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
25582558
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v12, (a1)
2559-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v16, v8, v12
2560-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v16
2559+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v12
2560+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
25612561
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
25622562
; CHECK-UNALIGNED-RV32-V-NEXT: ret
25632563
;
@@ -2567,8 +2567,8 @@ define i32 @bcmp_size_64(ptr %s1, ptr %s2) nounwind {
25672567
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
25682568
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
25692569
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v12, (a1)
2570-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v16, v8, v12
2571-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v16
2570+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v12
2571+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
25722572
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
25732573
; CHECK-UNALIGNED-RV64-V-NEXT: ret
25742574
entry:
@@ -2723,8 +2723,8 @@ define i32 @bcmp_size_127(ptr %s1, ptr %s2) nounwind {
27232723
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
27242724
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
27252725
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v16, (a1)
2726-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v24, v8, v16
2727-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v24
2726+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v16
2727+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
27282728
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
27292729
; CHECK-UNALIGNED-RV32-V-NEXT: ret
27302730
;
@@ -2734,8 +2734,8 @@ define i32 @bcmp_size_127(ptr %s1, ptr %s2) nounwind {
27342734
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
27352735
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
27362736
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v16, (a1)
2737-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v24, v8, v16
2738-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v24
2737+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v16
2738+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
27392739
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
27402740
; CHECK-UNALIGNED-RV64-V-NEXT: ret
27412741
entry:
@@ -2890,8 +2890,8 @@ define i32 @bcmp_size_128(ptr %s1, ptr %s2) nounwind {
28902890
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
28912891
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
28922892
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v16, (a1)
2893-
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v24, v8, v16
2894-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v24
2893+
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v16
2894+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
28952895
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
28962896
; CHECK-UNALIGNED-RV32-V-NEXT: ret
28972897
;
@@ -2901,8 +2901,8 @@ define i32 @bcmp_size_128(ptr %s1, ptr %s2) nounwind {
29012901
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
29022902
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
29032903
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v16, (a1)
2904-
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v24, v8, v16
2905-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v24
2904+
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v8, v8, v16
2905+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v8
29062906
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
29072907
; CHECK-UNALIGNED-RV64-V-NEXT: ret
29082908
entry:

‎llvm/test/CodeGen/RISCV/pr94265.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,8 @@ define <8 x i16> @PR94265(<8 x i32> %a0) #0 {
1212
; RV32I-NEXT: vsrl.vi v10, v10, 26
1313
; RV32I-NEXT: vadd.vv v8, v8, v10
1414
; RV32I-NEXT: vsetvli zero, zero, e16, m1, ta, ma
15-
; RV32I-NEXT: vnsrl.wi v10, v8, 6
16-
; RV32I-NEXT: vsll.vi v8, v10, 10
15+
; RV32I-NEXT: vnsrl.wi v8, v8, 6
16+
; RV32I-NEXT: vsll.vi v8, v8, 10
1717
; RV32I-NEXT: ret
1818
;
1919
; RV64I-LABEL: PR94265:
@@ -23,8 +23,8 @@ define <8 x i16> @PR94265(<8 x i32> %a0) #0 {
2323
; RV64I-NEXT: vsrl.vi v10, v10, 26
2424
; RV64I-NEXT: vadd.vv v8, v8, v10
2525
; RV64I-NEXT: vsetvli zero, zero, e16, m1, ta, ma
26-
; RV64I-NEXT: vnsrl.wi v10, v8, 6
27-
; RV64I-NEXT: vsll.vi v8, v10, 10
26+
; RV64I-NEXT: vnsrl.wi v8, v8, 6
27+
; RV64I-NEXT: vsll.vi v8, v8, 10
2828
; RV64I-NEXT: ret
2929
%t1 = sdiv <8 x i32> %a0, <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64>
3030
%t2 = trunc <8 x i32> %t1 to <8 x i16>

‎llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -49,13 +49,13 @@ define void @last_chance_recoloring_failure() {
4949
; CHECK-NEXT: addi a0, a0, 16
5050
; CHECK-NEXT: csrr a1, vlenb
5151
; CHECK-NEXT: slli a1, a1, 2
52-
; CHECK-NEXT: vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
52+
; CHECK-NEXT: vl4r.v v12, (a0) # vscale x 32-byte Folded Reload
5353
; CHECK-NEXT: add a0, a0, a1
54-
; CHECK-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
54+
; CHECK-NEXT: vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
5555
; CHECK-NEXT: addi a0, sp, 16
5656
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
5757
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
58-
; CHECK-NEXT: vfwsub.wv v8, v24, v16
58+
; CHECK-NEXT: vfwsub.wv v8, v24, v12
5959
; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, mu
6060
; CHECK-NEXT: vfdiv.vv v8, v24, v8, v0.t
6161
; CHECK-NEXT: vse32.v v8, (a0)
@@ -109,15 +109,15 @@ define void @last_chance_recoloring_failure() {
109109
; SUBREGLIVENESS-NEXT: addi a0, a0, 16
110110
; SUBREGLIVENESS-NEXT: csrr a1, vlenb
111111
; SUBREGLIVENESS-NEXT: slli a1, a1, 2
112-
; SUBREGLIVENESS-NEXT: vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
112+
; SUBREGLIVENESS-NEXT: vl4r.v v12, (a0) # vscale x 32-byte Folded Reload
113113
; SUBREGLIVENESS-NEXT: add a0, a0, a1
114-
; SUBREGLIVENESS-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
114+
; SUBREGLIVENESS-NEXT: vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
115115
; SUBREGLIVENESS-NEXT: addi a0, sp, 16
116-
; SUBREGLIVENESS-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
116+
; SUBREGLIVENESS-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
117117
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
118-
; SUBREGLIVENESS-NEXT: vfwsub.wv v8, v24, v16
118+
; SUBREGLIVENESS-NEXT: vfwsub.wv v8, v16, v12
119119
; SUBREGLIVENESS-NEXT: vsetvli zero, zero, e32, m8, tu, mu
120-
; SUBREGLIVENESS-NEXT: vfdiv.vv v8, v24, v8, v0.t
120+
; SUBREGLIVENESS-NEXT: vfdiv.vv v8, v16, v8, v0.t
121121
; SUBREGLIVENESS-NEXT: vse32.v v8, (a0)
122122
; SUBREGLIVENESS-NEXT: csrr a0, vlenb
123123
; SUBREGLIVENESS-NEXT: slli a0, a0, 4

0 commit comments

Comments
 (0)