Make new AArch64ISD nodes return f32

Author: mrkajetanp

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -2538,7 +2538,8 @@ void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
 }
 
 // Select f16 -> i16 conversions
-// Since i16 is an illegal type, they need to return an i32 result
+// Since i16 is an illegal type, we return the converted bit pattern in a f32
+// which can then be bitcast to i32 and truncated as needed.
 void AArch64DAGToDAGISel::SelectFCVT_FPTOINT_Half(SDNode *N, unsigned int Opc) {
   SDLoc DL(N);
   SDValue SrcVal = N->getOperand(0);
@@ -2551,9 +2552,7 @@ void AArch64DAGToDAGISel::SelectFCVT_FPTOINT_Half(SDNode *N, unsigned int Opc) {
   SDNode *Extract =
       CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f32,
                              SDValue(SubregToReg, 0), Ssub);
-  SDNode *Result = CurDAG->getMachineNode(AArch64::FMOVSWr, DL, MVT::i32,
-                                          SDValue(Extract, 0));
-  ReplaceNode(N, Result);
+  ReplaceNode(N, Extract);
 }
 
 static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -4912,9 +4912,12 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
     return SDValue();
 
   if (SrcVT == MVT::f16 && SatVT == MVT::i16 && DstVT == MVT::i32) {
+    SDValue CVTf32;
     if (Op.getOpcode() == ISD::FP_TO_SINT_SAT)
-      return DAG.getNode(AArch64ISD::FCVTZS_HALF, DL, DstVT, SrcVal);
-    return DAG.getNode(AArch64ISD::FCVTZU_HALF, DL, DstVT, SrcVal);
+      CVTf32 = DAG.getNode(AArch64ISD::FCVTZS_HALF, DL, MVT::f32, SrcVal);
+    else
+      CVTf32 = DAG.getNode(AArch64ISD::FCVTZU_HALF, DL, MVT::f32, SrcVal);
+    return DAG.getBitcast(DstVT, CVTf32);
   }
 
   SDValue NativeCvt =

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -989,8 +989,8 @@ def AArch64fcvtxnv: PatFrags<(ops node:$Rn),
                                  [(int_aarch64_neon_fcvtxn node:$Rn),
                                   (AArch64fcvtxn_n node:$Rn)]>;
 
-def AArch64fcvtzs_half : SDNode<"AArch64ISD::FCVTZS_HALF", SDTFPToIntOp>;
-def AArch64fcvtzu_half : SDNode<"AArch64ISD::FCVTZU_HALF", SDTFPToIntOp>;
+def AArch64fcvtzs_half : SDNode<"AArch64ISD::FCVTZS_HALF", SDTFPExtendOp>;
+def AArch64fcvtzu_half : SDNode<"AArch64ISD::FCVTZU_HALF", SDTFPExtendOp>;
 
 //def Aarch64softf32tobf16v8: SDNode<"AArch64ISD::", SDTFPRoundOp>;