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[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5 [skip ci]
1 parent 904fd88 commit e0f99c4

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4 files changed

+313
-168
lines changed

4 files changed

+313
-168
lines changed

llvm/lib/Target/Sparc/SparcISelLowering.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
#include "llvm/CodeGen/MachineRegisterInfo.h"
2828
#include "llvm/CodeGen/SelectionDAG.h"
2929
#include "llvm/CodeGen/SelectionDAGNodes.h"
30+
#include "llvm/CodeGen/TargetLowering.h"
3031
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
3132
#include "llvm/IR/DerivedTypes.h"
3233
#include "llvm/IR/DiagnosticInfo.h"

llvm/lib/Target/Sparc/SparcInstrVIS.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -279,8 +279,8 @@ def XMULXHI : VISInst<0b100010110, "xmulxhi", I64Regs>;
279279
} // Predicates = [IsVIS3]
280280

281281
// FP immediate patterns.
282-
def fpimm0 : PatLeaf<(fpimm), [{return N->isExactlyValue(+0.0);}]>;
283-
def fpnegimm0 : PatLeaf<(fpimm), [{return N->isExactlyValue(-0.0);}]>;
282+
def fpimm0 : FPImmLeaf<fAny, [{return Imm.isExactlyValue(+0.0);}]>;
283+
def fpnegimm0 : FPImmLeaf<fAny, [{return Imm.isExactlyValue(-0.0);}]>;
284284

285285
// VIS instruction patterns.
286286
let Predicates = [HasVIS] in {
@@ -311,7 +311,7 @@ def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>;
311311
def : Pat<(i32 (ctlz i32:$src)), (ADDri (LZCNT (SRLri $src, 0)), (i32 -32))>;
312312

313313
def : Pat<(i32 (bitconvert f32:$src)), (MOVSTOUW $src)>;
314-
def : Pat<(i64 (zext (i32 (bitconvert f32:$src)))), (MOVSTOUW $src)>;
314+
def : Pat<(i64 (zanyext (i32 (bitconvert f32:$src)))), (MOVSTOUW $src)>;
315315
def : Pat<(i64 (sext (i32 (bitconvert f32:$src)))), (MOVSTOSW $src)>;
316316
def : Pat<(f32 (bitconvert i32:$src)), (MOVWTOS $src)>;
317317
def : Pat<(i64 (bitconvert f64:$src)), (MOVDTOX $src)>;

llvm/test/CodeGen/SPARC/bitcast.ll

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9
33
; RUN: llc < %s -mtriple=sparcv9 -mattr=vis3 | FileCheck %s -check-prefix=VIS3
44

5-
define i32 @stow(float %0) nounwind {
5+
define i32 @stow(float %float) nounwind {
66
; V9-LABEL: stow:
77
; V9: ! %bb.0:
88
; V9-NEXT: add %sp, -144, %sp
@@ -15,11 +15,11 @@ define i32 @stow(float %0) nounwind {
1515
; VIS3: ! %bb.0:
1616
; VIS3-NEXT: retl
1717
; VIS3-NEXT: movstouw %f1, %o0
18-
%2 = bitcast float %0 to i32
19-
ret i32 %2
18+
%w = bitcast float %float to i32
19+
ret i32 %w
2020
}
2121

22-
define zeroext i32 @stouw(float %0) nounwind {
22+
define zeroext i32 @stouw(float %float) nounwind {
2323
; V9-LABEL: stouw:
2424
; V9: ! %bb.0:
2525
; V9-NEXT: add %sp, -144, %sp
@@ -32,11 +32,11 @@ define zeroext i32 @stouw(float %0) nounwind {
3232
; VIS3: ! %bb.0:
3333
; VIS3-NEXT: retl
3434
; VIS3-NEXT: movstouw %f1, %o0
35-
%2 = bitcast float %0 to i32
36-
ret i32 %2
35+
%uw = bitcast float %float to i32
36+
ret i32 %uw
3737
}
3838

39-
define signext i32 @stosw(float %0) nounwind {
39+
define signext i32 @stosw(float %float) nounwind {
4040
; V9-LABEL: stosw:
4141
; V9: ! %bb.0:
4242
; V9-NEXT: add %sp, -144, %sp
@@ -49,11 +49,11 @@ define signext i32 @stosw(float %0) nounwind {
4949
; VIS3: ! %bb.0:
5050
; VIS3-NEXT: retl
5151
; VIS3-NEXT: movstosw %f1, %o0
52-
%2 = bitcast float %0 to i32
53-
ret i32 %2
52+
%sw = bitcast float %float to i32
53+
ret i32 %sw
5454
}
5555

56-
define float @wtos(i32 %0) nounwind {
56+
define float @wtos(i32 %w) nounwind {
5757
; V9-LABEL: wtos:
5858
; V9: ! %bb.0:
5959
; V9-NEXT: add %sp, -144, %sp
@@ -66,11 +66,11 @@ define float @wtos(i32 %0) nounwind {
6666
; VIS3: ! %bb.0:
6767
; VIS3-NEXT: retl
6868
; VIS3-NEXT: movwtos %o0, %f0
69-
%2 = bitcast i32 %0 to float
70-
ret float %2
69+
%float = bitcast i32 %w to float
70+
ret float %float
7171
}
7272

73-
define float @uwtos(i32 zeroext %0) nounwind {
73+
define float @uwtos(i32 zeroext %uw) nounwind {
7474
; V9-LABEL: uwtos:
7575
; V9: ! %bb.0:
7676
; V9-NEXT: add %sp, -144, %sp
@@ -83,11 +83,11 @@ define float @uwtos(i32 zeroext %0) nounwind {
8383
; VIS3: ! %bb.0:
8484
; VIS3-NEXT: retl
8585
; VIS3-NEXT: movwtos %o0, %f0
86-
%2 = bitcast i32 %0 to float
87-
ret float %2
86+
%float = bitcast i32 %uw to float
87+
ret float %float
8888
}
8989

90-
define float @swtos(i32 signext %0) nounwind {
90+
define float @swtos(i32 signext %sw) nounwind {
9191
; V9-LABEL: swtos:
9292
; V9: ! %bb.0:
9393
; V9-NEXT: add %sp, -144, %sp
@@ -100,11 +100,11 @@ define float @swtos(i32 signext %0) nounwind {
100100
; VIS3: ! %bb.0:
101101
; VIS3-NEXT: retl
102102
; VIS3-NEXT: movwtos %o0, %f0
103-
%2 = bitcast i32 %0 to float
104-
ret float %2
103+
%float = bitcast i32 %sw to float
104+
ret float %float
105105
}
106106

107-
define i64 @dtox(double %0) nounwind {
107+
define i64 @dtox(double %double) nounwind {
108108
; V9-LABEL: dtox:
109109
; V9: ! %bb.0:
110110
; V9-NEXT: add %sp, -144, %sp
@@ -117,11 +117,11 @@ define i64 @dtox(double %0) nounwind {
117117
; VIS3: ! %bb.0:
118118
; VIS3-NEXT: retl
119119
; VIS3-NEXT: movdtox %f0, %o0
120-
%2 = bitcast double %0 to i64
121-
ret i64 %2
120+
%x = bitcast double %double to i64
121+
ret i64 %x
122122
}
123123

124-
define double @xtod(i64 %0) nounwind {
124+
define double @xtod(i64 %x) nounwind {
125125
; V9-LABEL: xtod:
126126
; V9: ! %bb.0:
127127
; V9-NEXT: add %sp, -144, %sp
@@ -134,6 +134,6 @@ define double @xtod(i64 %0) nounwind {
134134
; VIS3: ! %bb.0:
135135
; VIS3-NEXT: retl
136136
; VIS3-NEXT: movxtod %o0, %f0
137-
%2 = bitcast i64 %0 to double
138-
ret double %2
137+
%double = bitcast i64 %x to double
138+
ret double %double
139139
}

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