Skip Zicond for FP sel when we need to split regs

This patch disables the Zicond optimization for floating-point selects
when the value type exceeds XLen (e.g., f64 on RV32 +zdinx).

In these cases, using Zicond requires handling split registers, which
results in a higher dynamic instruction count compared to the standard
branch-based lowering (e.g., ~8 instructions vs ~5-7 instructions for
appended sample code).
Thus, there is no benefit to using Zicond here

```asm
define double @select_f64_fcmp(double %a, double %b,
  double %c, double %d) nounwind {
entry:
  %cmp = fcmp ogt double %a, %b
  %sel = select i1 %cmp, double %c, double %d
  ret double %sel
}
```

Branch version: Executes 5 or 7 instruction

```asm
; RV32ZDINX_NOZICOND-LABEL: select_f64_fcmp:
; RV32ZDINX_NOZICOND:       # %bb.0: # %entry
; RV32ZDINX_NOZICOND-NEXT:    flt.d a0, a2, a0
; RV32ZDINX_NOZICOND-NEXT:    bnez a0, .LBB2_2
; RV32ZDINX_NOZICOND-NEXT:  # %bb.1: # %entry
; RV32ZDINX_NOZICOND-NEXT:    mv a4, a6
; RV32ZDINX_NOZICOND-NEXT:    mv a5, a7
; RV32ZDINX_NOZICOND-NEXT:  .LBB2_2: # %entry
; RV32ZDINX_NOZICOND-NEXT:    mv a0, a4
; RV32ZDINX_NOZICOND-NEXT:    mv a1, a5
; RV32ZDINX_NOZICOND-NEXT:    ret
```

Zicond version: Always executes 8 instructions.

```asm
; RV32ZDINX_ZICOND-LABEL: select_f64_fcmp:
; RV32ZDINX_ZICOND:       # %bb.0: # %entry
; RV32ZDINX_ZICOND-NEXT:    flt.d a0, a2, a0
; RV32ZDINX_ZICOND-NEXT:    czero.nez a1, a6, a0
; RV32ZDINX_ZICOND-NEXT:    czero.eqz a2, a4, a0
; RV32ZDINX_ZICOND-NEXT:    czero.nez a3, a7, a0
; RV32ZDINX_ZICOND-NEXT:    czero.eqz a4, a5, a0
; RV32ZDINX_ZICOND-NEXT:    or a0, a2, a1
; RV32ZDINX_ZICOND-NEXT:    or a1, a4, a3
; RV32ZDINX_ZICOND-NEXT:    ret
```

Author: fennecJ

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -9558,31 +9558,16 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
   // When there is no cost for GPR <-> FGPR, we can use zicond select for
   // floating value when CondV is int type
   bool FPinGPR = Subtarget.hasStdExtZfinx();
-  bool UseZicondForFPSel =
-      Subtarget.hasStdExtZicond() && FPinGPR && VT.isFloatingPoint();
 
-  if (UseZicondForFPSel) {
-    MVT XLenIntVT = Subtarget.getXLenVT();
-
-    // Handle RV32 with f64 (Zdinx): Split into two 32-bit integer selects.
-    if (VT == MVT::f64 && !Subtarget.is64Bit()) {
-      SDValue TrueSplit = DAG.getNode(RISCVISD::SplitF64, DL,
-                                      DAG.getVTList(MVT::i32, MVT::i32), TrueV);
-      SDValue FalseSplit = DAG.getNode(
-          RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), FalseV);
-
-      SDValue TrueLo = TrueSplit.getValue(0);
-      SDValue TrueHi = TrueSplit.getValue(1);
-      SDValue FalseLo = FalseSplit.getValue(0);
-      SDValue FalseHi = FalseSplit.getValue(1);
+  // We can handle FGPR without spliting into hi/lo parts
+  bool FitsInGPR = TypeSize::isKnownLE(VT.getSizeInBits(),
+                                       Subtarget.getXLenVT().getSizeInBits());
 
-      SDValue ResLo =
-          DAG.getNode(ISD::SELECT, DL, MVT::i32, CondV, TrueLo, FalseLo);
-      SDValue ResHi =
-          DAG.getNode(ISD::SELECT, DL, MVT::i32, CondV, TrueHi, FalseHi);
+  bool UseZicondForFPSel = Subtarget.hasStdExtZicond() && FPinGPR &&
+                           VT.isFloatingPoint() && FitsInGPR;
 
-      return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, ResLo, ResHi);
-    }
+  if (UseZicondForFPSel) {
+    MVT XLenIntVT = Subtarget.getXLenVT();
 
     auto CastToInt = [&](SDValue V) -> SDValue {
       if (VT == MVT::f16)

llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll

@@ -178,12 +178,19 @@ define double @select_f64_i1(i1 %cond, double %t, double %f) nounwind {
 ; RV32ZDINX_ZICOND-LABEL: select_f64_i1:
 ; RV32ZDINX_ZICOND:       # %bb.0: # %entry
 ; RV32ZDINX_ZICOND-NEXT:    andi a0, a0, 1
-; RV32ZDINX_ZICOND-NEXT:    czero.nez a3, a3, a0
-; RV32ZDINX_ZICOND-NEXT:    czero.eqz a1, a1, a0
-; RV32ZDINX_ZICOND-NEXT:    czero.nez a4, a4, a0
-; RV32ZDINX_ZICOND-NEXT:    czero.eqz a2, a2, a0
-; RV32ZDINX_ZICOND-NEXT:    or a0, a1, a3
-; RV32ZDINX_ZICOND-NEXT:    or a1, a2, a4
+; RV32ZDINX_ZICOND-NEXT:    bnez a0, .LBB1_2
+; RV32ZDINX_ZICOND-NEXT:  # %bb.1: # %entry
+; RV32ZDINX_ZICOND-NEXT:    mv a7, a4
+; RV32ZDINX_ZICOND-NEXT:    mv a6, a3
+; RV32ZDINX_ZICOND-NEXT:    mv a4, a6
+; RV32ZDINX_ZICOND-NEXT:    mv a5, a7
+; RV32ZDINX_ZICOND-NEXT:    j .LBB1_3
+; RV32ZDINX_ZICOND-NEXT:  .LBB1_2:
+; RV32ZDINX_ZICOND-NEXT:    mv a5, a2
+; RV32ZDINX_ZICOND-NEXT:    mv a4, a1
+; RV32ZDINX_ZICOND-NEXT:  .LBB1_3: # %entry
+; RV32ZDINX_ZICOND-NEXT:    mv a0, a4
+; RV32ZDINX_ZICOND-NEXT:    mv a1, a5
 ; RV32ZDINX_ZICOND-NEXT:    ret
 ;
 ; RV32ZDINX_NOZICOND-LABEL: select_f64_i1:
@@ -319,12 +326,13 @@ define double @select_f64_fcmp(double %a, double %b, double %c, double %d) nounw
 ; RV32ZDINX_ZICOND-LABEL: select_f64_fcmp:
 ; RV32ZDINX_ZICOND:       # %bb.0: # %entry
 ; RV32ZDINX_ZICOND-NEXT:    flt.d a0, a2, a0
-; RV32ZDINX_ZICOND-NEXT:    czero.nez a1, a6, a0
-; RV32ZDINX_ZICOND-NEXT:    czero.eqz a2, a4, a0
-; RV32ZDINX_ZICOND-NEXT:    czero.nez a3, a7, a0
-; RV32ZDINX_ZICOND-NEXT:    czero.eqz a4, a5, a0
-; RV32ZDINX_ZICOND-NEXT:    or a0, a2, a1
-; RV32ZDINX_ZICOND-NEXT:    or a1, a4, a3
+; RV32ZDINX_ZICOND-NEXT:    bnez a0, .LBB2_2
+; RV32ZDINX_ZICOND-NEXT:  # %bb.1: # %entry
+; RV32ZDINX_ZICOND-NEXT:    mv a4, a6
+; RV32ZDINX_ZICOND-NEXT:    mv a5, a7
+; RV32ZDINX_ZICOND-NEXT:  .LBB2_2: # %entry
+; RV32ZDINX_ZICOND-NEXT:    mv a0, a4
+; RV32ZDINX_ZICOND-NEXT:    mv a1, a5
 ; RV32ZDINX_ZICOND-NEXT:    ret
 ;
 ; RV32ZDINX_NOZICOND-LABEL: select_f64_fcmp: