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[PowerPC]: Updated tests
1 parent 643e4d5 commit e2032ef

11 files changed

+268
-72
lines changed

‎llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
12
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
23
; RUN: grep eqv | count 3
34
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | \

‎llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll‎

Lines changed: 10 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -113,14 +113,12 @@ define i32 @test_f32_ord_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
113113
define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
114114
; SPE-LABEL: test_f32_ueq_s:
115115
; SPE: # %bb.0:
116-
; SPE-NEXT: efscmplt cr0, r5, r6
117-
; SPE-NEXT: bc 12, gt, .LBB7_3
118-
; SPE-NEXT: # %bb.1:
119116
; SPE-NEXT: efscmpgt cr0, r5, r6
120-
; SPE-NEXT: bc 12, gt, .LBB7_3
121-
; SPE-NEXT: # %bb.2:
122-
; SPE-NEXT: mr r4, r3
123-
; SPE-NEXT: .LBB7_3:
117+
; SPE-NEXT: bc 12, gt, .LBB7_2
118+
; SPE-NEXT: # %bb.1:
119+
; SPE-NEXT: efscmplt cr0, r5, r6
120+
; SPE-NEXT: bclr 4, gt, 0
121+
; SPE-NEXT: .LBB7_2:
124122
; SPE-NEXT: mr r3, r4
125123
; SPE-NEXT: blr
126124
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ueq", metadata !"fpexcept.strict") #0
@@ -355,14 +353,12 @@ define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
355353
; SPE: # %bb.0:
356354
; SPE-NEXT: evmergelo r7, r7, r8
357355
; SPE-NEXT: evmergelo r5, r5, r6
358-
; SPE-NEXT: efdcmplt cr0, r5, r7
359-
; SPE-NEXT: bc 12, gt, .LBB21_3
360-
; SPE-NEXT: # %bb.1:
361356
; SPE-NEXT: efdcmpgt cr0, r5, r7
362-
; SPE-NEXT: bc 12, gt, .LBB21_3
363-
; SPE-NEXT: # %bb.2:
364-
; SPE-NEXT: mr r4, r3
365-
; SPE-NEXT: .LBB21_3:
357+
; SPE-NEXT: bc 12, gt, .LBB21_2
358+
; SPE-NEXT: # %bb.1:
359+
; SPE-NEXT: efdcmplt cr0, r5, r7
360+
; SPE-NEXT: bclr 4, gt, 0
361+
; SPE-NEXT: .LBB21_2:
366362
; SPE-NEXT: mr r3, r4
367363
; SPE-NEXT: blr
368364
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ueq", metadata !"fpexcept.strict") #0

‎llvm/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll‎

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,38 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
12
; Check the miscellaneous logical vector operations added in P8
2-
;
3+
;
34
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
45
; Test x eqv y
56
define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
7+
; CHECK-LABEL: test_veqv:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: veqv 2, 2, 3
10+
; CHECK-NEXT: blr
611
%tmp = xor <4 x i32> %x, %y
712
%ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
813
ret <4 x i32> %ret_val
9-
; CHECK: veqv 2, 2, 3
1014
}
1115

1216
; Test x vnand y
1317
define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind {
18+
; CHECK-LABEL: test_vnand:
19+
; CHECK: # %bb.0:
20+
; CHECK-NEXT: vnand 2, 2, 3
21+
; CHECK-NEXT: blr
1422
%tmp = and <4 x i32> %x, %y
1523
%ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
1624
ret <4 x i32> %ret_val
17-
; CHECK: vnand 2, 2, 3
1825
}
1926

2027
; Test x vorc y and variants
2128
define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind {
29+
; CHECK-LABEL: test_vorc:
30+
; CHECK: # %bb.0:
31+
; CHECK-NEXT: vor 2, 3, 2
32+
; CHECK-NEXT: blr
2233
%tmp1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
2334
%tmp2 = or <4 x i32> %x, %tmp1
24-
; CHECK: vorc 3, 2, 3
2535
%tmp3 = xor <4 x i32> %tmp2, <i32 -1, i32 -1, i32 -1, i32 -1>
2636
%tmp4 = or <4 x i32> %tmp3, %x
27-
; CHECK: vorc 2, 2, 3
2837
ret <4 x i32> %tmp4
2938
}

‎llvm/test/CodeGen/PowerPC/xxeval-and-nand.ll‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
12
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
23
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
34

@@ -6,6 +7,10 @@
67
; CHECK: xxlandc v2, v2, v3
78
; CHECK-NEXT: blr
89
define dso_local <4 x i32> @and_not(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
10+
; CHECK-LABEL: and_not:
11+
; CHECK: # %bb.0: # %entry
12+
; CHECK-NEXT: xxlandc v2, v2, v3
13+
; CHECK-NEXT: blr
914
entry:
1015
%neg = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>
1116
%and = and <4 x i32> %neg, %A
@@ -17,6 +22,10 @@ entry:
1722
; CHECK: xxeval v2, v3, v2, v4, 1
1823
; CHECK-NEXT: blr
1924
define dso_local <16 x i8> @and_and8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) local_unnamed_addr #0 {
25+
; CHECK-LABEL: and_and8:
26+
; CHECK: # %bb.0: # %entry
27+
; CHECK-NEXT: xxeval v2, v3, v2, v4, 1
28+
; CHECK-NEXT: blr
2029
entry:
2130
%and = and <16 x i8> %B, %A
2231
%and1 = and <16 x i8> %and, %C
@@ -28,6 +37,10 @@ entry:
2837
; CHECK: xxeval v2, v3, v2, v4, 1
2938
; CHECK-NEXT: blr
3039
define dso_local <8 x i16> @and_and16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) local_unnamed_addr #0 {
40+
; CHECK-LABEL: and_and16:
41+
; CHECK: # %bb.0: # %entry
42+
; CHECK-NEXT: xxeval v2, v3, v2, v4, 1
43+
; CHECK-NEXT: blr
3144
entry:
3245
%and = and <8 x i16> %B, %A
3346
%and1 = and <8 x i16> %and, %C
@@ -39,6 +52,10 @@ entry:
3952
; CHECK: xxeval v2, v3, v2, v4, 1
4053
; CHECK-NEXT: blr
4154
define dso_local <4 x i32> @and_and32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
55+
; CHECK-LABEL: and_and32:
56+
; CHECK: # %bb.0: # %entry
57+
; CHECK-NEXT: xxeval v2, v3, v2, v4, 1
58+
; CHECK-NEXT: blr
4259
entry:
4360
%and = and <4 x i32> %B, %A
4461
%and1 = and <4 x i32> %and, %C
@@ -50,6 +67,10 @@ entry:
5067
; CHECK: xxeval v2, v3, v2, v4, 1
5168
; CHECK-NEXT: blr
5269
define dso_local <2 x i64> @and_and64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
70+
; CHECK-LABEL: and_and64:
71+
; CHECK: # %bb.0: # %entry
72+
; CHECK-NEXT: xxeval v2, v3, v2, v4, 1
73+
; CHECK-NEXT: blr
5374
entry:
5475
%and = and <2 x i64> %B, %A
5576
%and1 = and <2 x i64> %and, %C
@@ -61,6 +82,10 @@ entry:
6182
; CHECK: xxeval v2, v2, v4, v3, 14
6283
; CHECK-NEXT: blr
6384
define dso_local <4 x i32> @and_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
85+
; CHECK-LABEL: and_nand:
86+
; CHECK: # %bb.0: # %entry
87+
; CHECK-NEXT: xxeval v2, v2, v4, v3, 14
88+
; CHECK-NEXT: blr
6489
entry:
6590
%and = and <4 x i32> %C, %B
6691
%neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -73,6 +98,10 @@ entry:
7398
; CHECK: xxeval v2, v2, v4, v3, 7
7499
; CHECK-NEXT: blr
75100
define dso_local <4 x i32> @and_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
101+
; CHECK-LABEL: and_or:
102+
; CHECK: # %bb.0: # %entry
103+
; CHECK-NEXT: xxeval v2, v2, v4, v3, 7
104+
; CHECK-NEXT: blr
76105
entry:
77106
%or = or <4 x i32> %C, %B
78107
%and = and <4 x i32> %or, %A
@@ -84,6 +113,10 @@ entry:
84113
; CHECK: xxeval v2, v2, v4, v3, 8
85114
; CHECK-NEXT: blr
86115
define dso_local <4 x i32> @and_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
116+
; CHECK-LABEL: and_nor:
117+
; CHECK: # %bb.0: # %entry
118+
; CHECK-NEXT: xxeval v2, v2, v4, v3, 8
119+
; CHECK-NEXT: blr
87120
entry:
88121
%or = or <4 x i32> %C, %B
89122
%neg = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -96,6 +129,10 @@ entry:
96129
; CHECK: xxeval v2, v2, v4, v3, 6
97130
; CHECK-NEXT: blr
98131
define dso_local <4 x i32> @and_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
132+
; CHECK-LABEL: and_xor:
133+
; CHECK: # %bb.0: # %entry
134+
; CHECK-NEXT: xxeval v2, v2, v4, v3, 6
135+
; CHECK-NEXT: blr
99136
entry:
100137
%xor = xor <4 x i32> %C, %B
101138
%and = and <4 x i32> %xor, %A
@@ -107,6 +144,10 @@ entry:
107144
; CHECK: xxeval v2, v2, v3, v4, 9
108145
; CHECK-NEXT: blr
109146
define dso_local <4 x i32> @and_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
147+
; CHECK-LABEL: and_eqv:
148+
; CHECK: # %bb.0: # %entry
149+
; CHECK-NEXT: xxeval v2, v2, v3, v4, 9
150+
; CHECK-NEXT: blr
110151
entry:
111152
%xor = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>
112153
%neg = xor <4 x i32> %xor, %C
@@ -119,6 +160,10 @@ entry:
119160
; CHECK: xxeval v2, v2, v4, v3, 241
120161
; CHECK-NEXT: blr
121162
define dso_local <4 x i32> @nand_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
163+
; CHECK-LABEL: nand_nand:
164+
; CHECK: # %bb.0: # %entry
165+
; CHECK-NEXT: xxeval v2, v2, v4, v3, 241
166+
; CHECK-NEXT: blr
122167
entry:
123168
%and = and <4 x i32> %C, %B
124169
%A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -131,6 +176,10 @@ entry:
131176
; CHECK: xxeval v2, v3, v2, v4, 254
132177
; CHECK-NEXT: blr
133178
define dso_local <4 x i32> @nand_and(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
179+
; CHECK-LABEL: nand_and:
180+
; CHECK: # %bb.0: # %entry
181+
; CHECK-NEXT: xxeval v2, v3, v2, v4, 254
182+
; CHECK-NEXT: blr
134183
entry:
135184
%and = and <4 x i32> %B, %A
136185
%and1 = and <4 x i32> %and, %C
@@ -143,6 +192,10 @@ entry:
143192
; CHECK: xxeval v2, v2, v4, v3, 249
144193
; CHECK-NEXT: blr
145194
define dso_local <4 x i32> @nand_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
195+
; CHECK-LABEL: nand_xor:
196+
; CHECK: # %bb.0: # %entry
197+
; CHECK-NEXT: xxeval v2, v2, v4, v3, 249
198+
; CHECK-NEXT: blr
146199
entry:
147200
%xor = xor <4 x i32> %C, %B
148201
%and = and <4 x i32> %xor, %A
@@ -155,6 +208,10 @@ entry:
155208
; CHECK: xxeval v2, v2, v4, v3, 246
156209
; CHECK-NEXT: blr
157210
define dso_local <4 x i32> @nand_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
211+
; CHECK-LABEL: nand_eqv:
212+
; CHECK: # %bb.0: # %entry
213+
; CHECK-NEXT: xxeval v2, v2, v4, v3, 246
214+
; CHECK-NEXT: blr
158215
entry:
159216
%xor = xor <4 x i32> %C, %B
160217
%A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -167,6 +224,10 @@ entry:
167224
; CHECK: xxeval v2, v2, v4, v3, 248
168225
; CHECK-NEXT: blr
169226
define dso_local <4 x i32> @nand_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
227+
; CHECK-LABEL: nand_or:
228+
; CHECK: # %bb.0: # %entry
229+
; CHECK-NEXT: xxeval v2, v2, v4, v3, 248
230+
; CHECK-NEXT: blr
170231
entry:
171232
%or = or <4 x i32> %C, %B
172233
%and = and <4 x i32> %or, %A
@@ -179,6 +240,10 @@ entry:
179240
; CHECK: xxeval v2, v2, v3, v4, 247
180241
; CHECK-NEXT: blr
181242
define dso_local <4 x i32> @nand_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
243+
; CHECK-LABEL: nand_nor:
244+
; CHECK: # %bb.0: # %entry
245+
; CHECK-NEXT: xxeval v2, v2, v3, v4, 247
246+
; CHECK-NEXT: blr
182247
entry:
183248
%A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
184249
%or = or <4 x i32> %A.not, %B

‎llvm/test/CodeGen/PowerPC/xxeval-eqv-nor-or-xor.ll‎

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,10 @@ entry:
3232
define dso_local <8 x i16> @eqvA_B_C(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) local_unnamed_addr #0 {
3333
; CHECK-LABEL: eqvA_B_C:
3434
; CHECK: # %bb.0: # %entry
35-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 150
35+
; CHECK-NEXT: xxleqv vs1, vs1, vs1
36+
; CHECK-NEXT: xxland vs0, v3, v4
37+
; CHECK-NEXT: xxeval vs1, v3, v4, vs1, 96
38+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
3639
; CHECK-NEXT: blr
3740
entry:
3841
%and = and <8 x i16> %B, %C
@@ -48,7 +51,8 @@ entry:
4851
define dso_local <16 x i8> @norA_andB_C(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) local_unnamed_addr #0 {
4952
; CHECK-LABEL: norA_andB_C:
5053
; CHECK: # %bb.0: # %entry
51-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 224
54+
; CHECK-NEXT: xxlnor vs0, v2, v2
55+
; CHECK-NEXT: xxeval v2, vs0, v3, v4, 14
5256
; CHECK-NEXT: blr
5357
entry:
5458
%and = and <16 x i8> %B, %C
@@ -100,7 +104,8 @@ entry:
100104
define dso_local <4 x i32> @norA_xorB_C(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
101105
; CHECK-LABEL: norA_xorB_C:
102106
; CHECK: # %bb.0: # %entry
103-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 144
107+
; CHECK-NEXT: xxlnor vs0, v2, v2
108+
; CHECK-NEXT: xxeval v2, vs0, v3, v4, 9
104109
; CHECK-NEXT: blr
105110
entry:
106111
%xor = xor <4 x i32> %B, %C
@@ -113,7 +118,9 @@ entry:
113118
define dso_local <4 x i32> @norA_B_C(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
114119
; CHECK-LABEL: norA_B_C:
115120
; CHECK: # %bb.0: # %entry
116-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 128
121+
; CHECK-NEXT: xxlnor vs0, v4, v4
122+
; CHECK-NEXT: xxlnor vs1, v3, v3
123+
; CHECK-NEXT: xxeval v2, v2, vs1, vs0, 16
117124
; CHECK-NEXT: blr
118125
entry:
119126
%or = or <4 x i32> %B, %C
@@ -164,7 +171,9 @@ entry:
164171
define dso_local <4 x i32> @orA_norB_C(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
165172
; CHECK-LABEL: orA_norB_C:
166173
; CHECK: # %bb.0: # %entry
167-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 143
174+
; CHECK-NEXT: xxlnor vs0, v4, v4
175+
; CHECK-NEXT: xxlnor vs1, v3, v3
176+
; CHECK-NEXT: xxeval v2, v2, vs1, vs0, 31
168177
; CHECK-NEXT: blr
169178
entry:
170179
%or = or <4 x i32> %B, %C

‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll‎

Lines changed: 15 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -80,9 +80,11 @@ define <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i
8080
; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32:
8181
; CHECK: # %bb.0: # %entry
8282
; CHECK-NEXT: xxleqv v5, v5, v5
83+
; CHECK-NEXT: xxland vs1, v3, v4
8384
; CHECK-NEXT: vslw v2, v2, v5
85+
; CHECK-NEXT: xxeval vs0, v3, v4, v5, 96
8486
; CHECK-NEXT: vsraw v2, v2, v5
85-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 24
87+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
8688
; CHECK-NEXT: blr
8789
entry:
8890
%or = or <4 x i32> %B, %C
@@ -97,10 +99,13 @@ define <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i
9799
; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64:
98100
; CHECK: # %bb.0: # %entry
99101
; CHECK-NEXT: xxlxor v5, v5, v5
102+
; CHECK-NEXT: xxleqv vs0, vs0, vs0
103+
; CHECK-NEXT: xxland vs1, v3, v4
100104
; CHECK-NEXT: xxsplti32dx v5, 1, 63
105+
; CHECK-NEXT: xxeval vs0, v3, v4, vs0, 96
101106
; CHECK-NEXT: vsld v2, v2, v5
102107
; CHECK-NEXT: vsrad v2, v2, v5
103-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 24
108+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
104109
; CHECK-NEXT: blr
105110
entry:
106111
%or = or <2 x i64> %B, %C
@@ -115,9 +120,12 @@ define <16 x i8> @ternary_A_nor_BC_and_BC_16x8(<16 x i1> %A, <16 x i8> %B, <16 x
115120
; CHECK-LABEL: ternary_A_nor_BC_and_BC_16x8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxspltib v5, 7
123+
; CHECK-NEXT: xxleqv vs0, vs0, vs0
124+
; CHECK-NEXT: xxland vs1, v3, v4
125+
; CHECK-NEXT: xxeval vs0, v3, v4, vs0, 96
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; CHECK-NEXT: vslb v2, v2, v5
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; CHECK-NEXT: vsrab v2, v2, v5
120-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 24
128+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
121129
; CHECK-NEXT: blr
122130
entry:
123131
%or = or <16 x i8> %B, %C
@@ -132,9 +140,12 @@ define <8 x i16> @ternary_A_nor_BC_and_BC_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i
132140
; CHECK-LABEL: ternary_A_nor_BC_and_BC_8x16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxspltiw v5, 983055
143+
; CHECK-NEXT: xxleqv vs0, vs0, vs0
144+
; CHECK-NEXT: xxland vs1, v3, v4
145+
; CHECK-NEXT: xxeval vs0, v3, v4, vs0, 96
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; CHECK-NEXT: vslh v2, v2, v5
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; CHECK-NEXT: vsrah v2, v2, v5
137-
; CHECK-NEXT: xxeval v2, v2, v3, v4, 24
148+
; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
139150
entry:
140151
%or = or <8 x i16> %B, %C

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