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[GISel][AArch64] Allow G_SEXT_INREG to be patterns to be imported.
SelectionDAG uses VTSDNode to store the extension type. GlobalISel uses a literal constant operand. For vectors, SelectionDAG uses a type with the same number of elements as other operand of the sext_inreg. I assume for GISel we would just use the scalar size.
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+58
-102
lines changed

13 files changed

+58
-102
lines changed

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ class GINodeEquiv<Instruction i, SDNode node> {
4848
// These are defined in the same order as the G_* instructions.
4949
def : GINodeEquiv<G_ANYEXT, anyext>;
5050
def : GINodeEquiv<G_SEXT, sext>;
51+
def : GINodeEquiv<G_SEXT_INREG, sext_inreg>;
5152
def : GINodeEquiv<G_ZEXT, zext>;
5253
def : GINodeEquiv<G_TRUNC, trunc>;
5354
def : GINodeEquiv<G_BITCAST, bitconvert>;

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp‎

Lines changed: 0 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,6 @@ class RISCVInstructionSelector : public InstructionSelector {
7676
bool materializeImm(Register Reg, int64_t Imm, MachineIRBuilder &MIB) const;
7777
bool selectAddr(MachineInstr &MI, MachineIRBuilder &MIB, bool IsLocal = true,
7878
bool IsExternWeak = false) const;
79-
bool selectSExtInreg(MachineInstr &MI, MachineIRBuilder &MIB) const;
8079
bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB) const;
8180
bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB) const;
8281
void emitFence(AtomicOrdering FenceOrdering, SyncScope::ID FenceSSID,
@@ -761,8 +760,6 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
761760
MI.setDesc(TII.get(RISCV::PseudoBRIND));
762761
MI.addOperand(MachineOperand::CreateImm(0));
763762
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
764-
case TargetOpcode::G_SEXT_INREG:
765-
return selectSExtInreg(MI, MIB);
766763
case TargetOpcode::G_FRAME_INDEX: {
767764
// TODO: We may want to replace this code with the SelectionDAG patterns,
768765
// which fail to get imported because it uses FrameAddrRegImm, which is a
@@ -1160,31 +1157,6 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI,
11601157
return false;
11611158
}
11621159

1163-
bool RISCVInstructionSelector::selectSExtInreg(MachineInstr &MI,
1164-
MachineIRBuilder &MIB) const {
1165-
Register DstReg = MI.getOperand(0).getReg();
1166-
Register SrcReg = MI.getOperand(1).getReg();
1167-
unsigned SrcSize = MI.getOperand(2).getImm();
1168-
1169-
MachineInstr *NewMI;
1170-
if (SrcSize == 32) {
1171-
assert(Subtarget->is64Bit() && "Unexpected extend");
1172-
// addiw rd, rs, 0 (i.e. sext.w rd, rs)
1173-
NewMI = MIB.buildInstr(RISCV::ADDIW, {DstReg}, {SrcReg}).addImm(0U);
1174-
} else {
1175-
assert(Subtarget->hasStdExtZbb() && "Unexpected extension");
1176-
assert((SrcSize == 8 || SrcSize == 16) && "Unexpected size");
1177-
unsigned Opc = SrcSize == 16 ? RISCV::SEXT_H : RISCV::SEXT_B;
1178-
NewMI = MIB.buildInstr(Opc, {DstReg}, {SrcReg});
1179-
}
1180-
1181-
if (!constrainSelectedInstRegOperands(*NewMI, TII, TRI, RBI))
1182-
return false;
1183-
1184-
MI.eraseFromParent();
1185-
return true;
1186-
}
1187-
11881160
bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
11891161
MachineIRBuilder &MIB) const {
11901162
auto &SelectMI = cast<GSelect>(MI);

‎llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,7 @@ define <8 x i16> @dupsext_v8i8_v8i16(i8 %src, <8 x i8> %b) {
1515
; CHECK-GI: // %bb.0: // %entry
1616
; CHECK-GI-NEXT: lsl w8, w0, #8
1717
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
18-
; CHECK-GI-NEXT: sxth w8, w8
19-
; CHECK-GI-NEXT: asr w8, w8, #8
18+
; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
2019
; CHECK-GI-NEXT: dup v1.8h, w8
2120
; CHECK-GI-NEXT: mul v0.8h, v1.8h, v0.8h
2221
; CHECK-GI-NEXT: ret
@@ -175,9 +174,8 @@ define <2 x i16> @dupsext_v2i8_v2i16(i8 %src, <2 x i8> %b) {
175174
; CHECK-GI: // %bb.0: // %entry
176175
; CHECK-GI-NEXT: lsl w8, w0, #8
177176
; CHECK-GI-NEXT: shl v0.2s, v0.2s, #24
178-
; CHECK-GI-NEXT: sxth w8, w8
177+
; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
179178
; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #24
180-
; CHECK-GI-NEXT: asr w8, w8, #8
181179
; CHECK-GI-NEXT: dup v1.4h, w8
182180
; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
183181
; CHECK-GI-NEXT: mul v0.2s, v1.2s, v0.2s
@@ -254,8 +252,7 @@ define <8 x i16> @nonsplat_shuffleinsert(i8 %src, <8 x i8> %b) {
254252
; CHECK-GI: // %bb.0: // %entry
255253
; CHECK-GI-NEXT: lsl w8, w0, #8
256254
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
257-
; CHECK-GI-NEXT: sxth w8, w8
258-
; CHECK-GI-NEXT: asr w8, w8, #8
255+
; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
259256
; CHECK-GI-NEXT: mov v1.h[1], w8
260257
; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #4
261258
; CHECK-GI-NEXT: mul v0.8h, v1.8h, v0.8h

‎llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -652,8 +652,7 @@ define i16 @red_mla_dup_ext_u8_s8_s16(ptr noalias nocapture noundef readonly %A,
652652
; CHECK-GI-NEXT: movi v0.2d, #0000000000000000
653653
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
654654
; CHECK-GI-NEXT: add x10, x0, #8
655-
; CHECK-GI-NEXT: sxth w9, w9
656-
; CHECK-GI-NEXT: asr w9, w9, #8
655+
; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
657656
; CHECK-GI-NEXT: dup v2.8h, w9
658657
; CHECK-GI-NEXT: and x9, x8, #0xfffffff0
659658
; CHECK-GI-NEXT: mov x11, x9

‎llvm/test/CodeGen/AArch64/arm64-mul.ll‎

Lines changed: 12 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -152,20 +152,12 @@ entry:
152152

153153
; Check the sext_inreg case.
154154
define i64 @t11(i64 %a) nounwind {
155-
; CHECK-SD-LABEL: t11:
156-
; CHECK-SD: // %bb.0: // %entry
157-
; CHECK-SD-NEXT: mov w8, #29594 // =0x739a
158-
; CHECK-SD-NEXT: movk w8, #65499, lsl #16
159-
; CHECK-SD-NEXT: smnegl x0, w0, w8
160-
; CHECK-SD-NEXT: ret
161-
;
162-
; CHECK-GI-LABEL: t11:
163-
; CHECK-GI: // %bb.0: // %entry
164-
; CHECK-GI-NEXT: sxtw x8, w0
165-
; CHECK-GI-NEXT: mov x9, #-35942 // =0xffffffffffff739a
166-
; CHECK-GI-NEXT: movk x9, #65499, lsl #16
167-
; CHECK-GI-NEXT: mneg x0, x8, x9
168-
; CHECK-GI-NEXT: ret
155+
; CHECK-LABEL: t11:
156+
; CHECK: // %bb.0: // %entry
157+
; CHECK-NEXT: mov w8, #29594 // =0x739a
158+
; CHECK-NEXT: movk w8, #65499, lsl #16
159+
; CHECK-NEXT: smnegl x0, w0, w8
160+
; CHECK-NEXT: ret
169161
entry:
170162
%tmp1 = trunc i64 %a to i32
171163
%tmp2 = sext i32 %tmp1 to i64
@@ -175,20 +167,12 @@ entry:
175167
}
176168

177169
define i64 @t12(i64 %a, i64 %b) nounwind {
178-
; CHECK-SD-LABEL: t12:
179-
; CHECK-SD: // %bb.0: // %entry
180-
; CHECK-SD-NEXT: mov w8, #35118 // =0x892e
181-
; CHECK-SD-NEXT: movk w8, #65008, lsl #16
182-
; CHECK-SD-NEXT: smaddl x0, w0, w8, x1
183-
; CHECK-SD-NEXT: ret
184-
;
185-
; CHECK-GI-LABEL: t12:
186-
; CHECK-GI: // %bb.0: // %entry
187-
; CHECK-GI-NEXT: sxtw x8, w0
188-
; CHECK-GI-NEXT: mov x9, #-30418 // =0xffffffffffff892e
189-
; CHECK-GI-NEXT: movk x9, #65008, lsl #16
190-
; CHECK-GI-NEXT: madd x0, x8, x9, x1
191-
; CHECK-GI-NEXT: ret
170+
; CHECK-LABEL: t12:
171+
; CHECK: // %bb.0: // %entry
172+
; CHECK-NEXT: mov w8, #35118 // =0x892e
173+
; CHECK-NEXT: movk w8, #65008, lsl #16
174+
; CHECK-NEXT: smaddl x0, w0, w8, x1
175+
; CHECK-NEXT: ret
192176
entry:
193177
%tmp1 = trunc i64 %a to i32
194178
%tmp2 = sext i32 %tmp1 to i64

‎llvm/test/CodeGen/AArch64/sadd_sat.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -71,9 +71,9 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
7171
; CHECK-GI-NEXT: sxth w8, w1
7272
; CHECK-GI-NEXT: add w8, w8, w0, sxth
7373
; CHECK-GI-NEXT: sxth w9, w8
74-
; CHECK-GI-NEXT: asr w10, w9, #15
75-
; CHECK-GI-NEXT: cmp w8, w9
74+
; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
7675
; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
76+
; CHECK-GI-NEXT: cmp w8, w9
7777
; CHECK-GI-NEXT: csel w0, w10, w8, ne
7878
; CHECK-GI-NEXT: ret
7979
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
@@ -98,9 +98,9 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
9898
; CHECK-GI-NEXT: sxtb w8, w1
9999
; CHECK-GI-NEXT: add w8, w8, w0, sxtb
100100
; CHECK-GI-NEXT: sxtb w9, w8
101-
; CHECK-GI-NEXT: asr w10, w9, #7
102-
; CHECK-GI-NEXT: cmp w8, w9
101+
; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
103102
; CHECK-GI-NEXT: sub w10, w10, #128
103+
; CHECK-GI-NEXT: cmp w8, w9
104104
; CHECK-GI-NEXT: csel w0, w10, w8, ne
105105
; CHECK-GI-NEXT: ret
106106
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);

‎llvm/test/CodeGen/AArch64/sadd_sat_plus.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -76,9 +76,9 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
7676
; CHECK-GI-NEXT: sxth w8, w8
7777
; CHECK-GI-NEXT: add w8, w8, w0, sxth
7878
; CHECK-GI-NEXT: sxth w9, w8
79-
; CHECK-GI-NEXT: asr w10, w9, #15
80-
; CHECK-GI-NEXT: cmp w8, w9
79+
; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
8180
; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
81+
; CHECK-GI-NEXT: cmp w8, w9
8282
; CHECK-GI-NEXT: csel w0, w10, w8, ne
8383
; CHECK-GI-NEXT: ret
8484
%a = mul i16 %y, %z
@@ -106,9 +106,9 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
106106
; CHECK-GI-NEXT: sxtb w8, w8
107107
; CHECK-GI-NEXT: add w8, w8, w0, sxtb
108108
; CHECK-GI-NEXT: sxtb w9, w8
109-
; CHECK-GI-NEXT: asr w10, w9, #7
110-
; CHECK-GI-NEXT: cmp w8, w9
109+
; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
111110
; CHECK-GI-NEXT: sub w10, w10, #128
111+
; CHECK-GI-NEXT: cmp w8, w9
112112
; CHECK-GI-NEXT: csel w0, w10, w8, ne
113113
; CHECK-GI-NEXT: ret
114114
%a = mul i8 %y, %z

‎llvm/test/CodeGen/AArch64/sadd_sat_vec.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -332,9 +332,9 @@ define void @v1i8(ptr %px, ptr %py, ptr %pz) nounwind {
332332
; CHECK-GI-NEXT: ldrsb w9, [x1]
333333
; CHECK-GI-NEXT: add w8, w8, w9
334334
; CHECK-GI-NEXT: sxtb w9, w8
335-
; CHECK-GI-NEXT: asr w10, w9, #7
336-
; CHECK-GI-NEXT: cmp w8, w9
335+
; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
337336
; CHECK-GI-NEXT: sub w10, w10, #128
337+
; CHECK-GI-NEXT: cmp w8, w9
338338
; CHECK-GI-NEXT: csel w8, w10, w8, ne
339339
; CHECK-GI-NEXT: strb w8, [x2]
340340
; CHECK-GI-NEXT: ret
@@ -360,9 +360,9 @@ define void @v1i16(ptr %px, ptr %py, ptr %pz) nounwind {
360360
; CHECK-GI-NEXT: ldrsh w9, [x1]
361361
; CHECK-GI-NEXT: add w8, w8, w9
362362
; CHECK-GI-NEXT: sxth w9, w8
363-
; CHECK-GI-NEXT: asr w10, w9, #15
364-
; CHECK-GI-NEXT: cmp w8, w9
363+
; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
365364
; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
365+
; CHECK-GI-NEXT: cmp w8, w9
366366
; CHECK-GI-NEXT: csel w8, w10, w8, ne
367367
; CHECK-GI-NEXT: strh w8, [x2]
368368
; CHECK-GI-NEXT: ret

‎llvm/test/CodeGen/AArch64/sext.ll‎

Lines changed: 8 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -221,14 +221,11 @@ define <3 x i16> @sext_v3i8_v3i16(<3 x i8> %a) {
221221
; CHECK-GI: // %bb.0: // %entry
222222
; CHECK-GI-NEXT: lsl w8, w0, #8
223223
; CHECK-GI-NEXT: lsl w9, w1, #8
224-
; CHECK-GI-NEXT: lsl w10, w2, #8
225-
; CHECK-GI-NEXT: sxth w8, w8
226-
; CHECK-GI-NEXT: sxth w9, w9
227-
; CHECK-GI-NEXT: asr w8, w8, #8
228-
; CHECK-GI-NEXT: asr w9, w9, #8
224+
; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
225+
; CHECK-GI-NEXT: sbfx w9, w9, #8, #8
229226
; CHECK-GI-NEXT: fmov s0, w8
230-
; CHECK-GI-NEXT: sxth w8, w10
231-
; CHECK-GI-NEXT: asr w8, w8, #8
227+
; CHECK-GI-NEXT: lsl w8, w2, #8
228+
; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
232229
; CHECK-GI-NEXT: mov v0.h[1], w9
233230
; CHECK-GI-NEXT: mov v0.h[2], w8
234231
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
@@ -386,14 +383,11 @@ define <3 x i16> @sext_v3i10_v3i16(<3 x i10> %a) {
386383
; CHECK-GI: // %bb.0: // %entry
387384
; CHECK-GI-NEXT: lsl w8, w0, #6
388385
; CHECK-GI-NEXT: lsl w9, w1, #6
389-
; CHECK-GI-NEXT: lsl w10, w2, #6
390-
; CHECK-GI-NEXT: sxth w8, w8
391-
; CHECK-GI-NEXT: sxth w9, w9
392-
; CHECK-GI-NEXT: asr w8, w8, #6
393-
; CHECK-GI-NEXT: asr w9, w9, #6
386+
; CHECK-GI-NEXT: sbfx w8, w8, #6, #10
387+
; CHECK-GI-NEXT: sbfx w9, w9, #6, #10
394388
; CHECK-GI-NEXT: fmov s0, w8
395-
; CHECK-GI-NEXT: sxth w8, w10
396-
; CHECK-GI-NEXT: asr w8, w8, #6
389+
; CHECK-GI-NEXT: lsl w8, w2, #6
390+
; CHECK-GI-NEXT: sbfx w8, w8, #6, #10
397391
; CHECK-GI-NEXT: mov v0.h[1], w9
398392
; CHECK-GI-NEXT: mov v0.h[2], w8
399393
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0

‎llvm/test/CodeGen/AArch64/ssub_sat.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -71,9 +71,9 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
7171
; CHECK-GI-NEXT: sxth w8, w0
7272
; CHECK-GI-NEXT: sub w8, w8, w1, sxth
7373
; CHECK-GI-NEXT: sxth w9, w8
74-
; CHECK-GI-NEXT: asr w10, w9, #15
75-
; CHECK-GI-NEXT: cmp w8, w9
74+
; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
7675
; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
76+
; CHECK-GI-NEXT: cmp w8, w9
7777
; CHECK-GI-NEXT: csel w0, w10, w8, ne
7878
; CHECK-GI-NEXT: ret
7979
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);
@@ -98,9 +98,9 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
9898
; CHECK-GI-NEXT: sxtb w8, w0
9999
; CHECK-GI-NEXT: sub w8, w8, w1, sxtb
100100
; CHECK-GI-NEXT: sxtb w9, w8
101-
; CHECK-GI-NEXT: asr w10, w9, #7
102-
; CHECK-GI-NEXT: cmp w8, w9
101+
; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
103102
; CHECK-GI-NEXT: sub w10, w10, #128
103+
; CHECK-GI-NEXT: cmp w8, w9
104104
; CHECK-GI-NEXT: csel w0, w10, w8, ne
105105
; CHECK-GI-NEXT: ret
106106
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);

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