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arjunUpatelarjunUpatel
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address comments, merge instruction evaluation and pass register width through constructor
1 parent 3fc4e31 commit e425a7c

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4 files changed

+86
-120
lines changed

4 files changed

+86
-120
lines changed

‎llvm/include/llvm/MC/MCInstrAnalysis.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#ifndef LLVM_MC_MCINSTRANALYSIS_H
1515
#define LLVM_MC_MCINSTRANALYSIS_H
1616

17+
#include "TargetRegistry.h"
1718
#include "llvm/ADT/ArrayRef.h"
1819
#include "llvm/MC/MCInst.h"
1920
#include "llvm/MC/MCInstrDesc.h"
@@ -185,7 +186,7 @@ class MCInstrAnalysis {
185186
/// the target address. Return true success, and the address in Target.
186187
virtual bool
187188
evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
188-
uint64_t &Target, int ArchRegWidth) const;
189+
uint64_t &Target, raw_ostream *TargetOS) const;
189190

190191
/// Given an instruction tries to get the address of a memory operand. Returns
191192
/// the address on success.

‎llvm/lib/MC/MCInstrAnalysis.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
3232

3333
bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst,
3434
uint64_t Addr, uint64_t Size,
35-
uint64_t &Target, int ArchRegWidth) const {
35+
uint64_t &Target, raw_ostream *TargetOS) const {
3636
return false;
3737
}
3838

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp‎

Lines changed: 80 additions & 113 deletions
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,7 @@ namespace {
127127
class RISCVMCInstrAnalysis : public MCInstrAnalysis {
128128
int64_t GPRState[31] = {};
129129
std::bitset<31> GPRValidMask;
130+
int ArchRegWidth;
130131

131132
static bool isGPR(MCRegister Reg) {
132133
return Reg >= RISCV::X0 && Reg <= RISCV::X31;
@@ -163,8 +164,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
163164
}
164165

165166
public:
166-
explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
167-
: MCInstrAnalysis(Info) {}
167+
explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info, int ArchRegWidth)
168+
: MCInstrAnalysis(Info), ArchRegWidth(ArchRegWidth) {}
168169

169170
void resetState() override { GPRValidMask.reset(); }
170171

@@ -180,35 +181,28 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
180181
}
181182

182183
switch (Inst.getOpcode()) {
183-
case RISCV::LUI: {
184-
setGPRState(Inst.getOperand(0).getReg(),
185-
SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
186-
break;
187-
}
188-
case RISCV::C_LUI: {
189-
MCRegister Reg = Inst.getOperand(0).getReg();
190-
if (Reg == RISCV::X2)
191-
break;
192-
setGPRState(Reg, SignExtend64<18>(Inst.getOperand(1).getImm() << 12));
193-
break;
194-
195-
}
196-
case RISCV::AUIPC: {
197-
setGPRState(Inst.getOperand(0).getReg(),
198-
Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
199-
break;
200-
}
201-
default: {
202-
// Clear the state of all defined registers for instructions that we don't
203-
// explicitly support.
204-
auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
205-
for (unsigned I = 0; I < NumDefs; ++I) {
206-
auto DefReg = Inst.getOperand(I).getReg();
207-
if (isGPR(DefReg))
208-
setGPRState(DefReg, std::nullopt);
209-
}
210-
break;
184+
case RISCV::C_LUI:
185+
case RISCV::LUI: {
186+
setGPRState(Inst.getOperand(0).getReg(),
187+
SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
188+
break;
189+
}
190+
case RISCV::AUIPC: {
191+
setGPRState(Inst.getOperand(0).getReg(),
192+
Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
193+
break;
194+
}
195+
default: {
196+
// Clear the state of all defined registers for instructions that we don't
197+
// explicitly support.
198+
auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
199+
for (unsigned I = 0; I < NumDefs; ++I) {
200+
auto DefReg = Inst.getOperand(I).getReg();
201+
if (isGPR(DefReg))
202+
setGPRState(DefReg, std::nullopt);
211203
}
204+
break;
205+
}
212206
}
213207
}
214208

@@ -247,90 +241,59 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
247241
}
248242

249243
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
250-
uint64_t &Target, int ArchRegWidth) const override {
244+
uint64_t &Target, raw_ostream *TargetOS) const override {
251245
switch(Inst.getOpcode()) {
252-
default:
253-
return false;
254-
case RISCV::ADDI: {
255-
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
256-
uint64_t Mask = ~((uint64_t)0) >> (64 - ArchRegWidth);
257-
Target = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
258-
Target &= Mask;
259-
return true;
260-
}
261-
break;
262-
}
263-
case RISCV::ADDIW: {
264-
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
265-
uint64_t Mask = ~((uint64_t)0) >> 32;
266-
Target = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
267-
Target &= Mask;
268-
Target = SignExtend64<32>(Target);
269-
return true;
270-
}
271-
break;
272-
}
273-
case RISCV::C_ADDI: {
274-
int64_t Offset = Inst.getOperand(2).getImm();
275-
if (Offset == 0)
276-
break;
277-
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
278-
Target = *TargetRegState + SignExtend64<6>(Offset);
279-
return true;
280-
}
281-
break;
282-
}
283-
case RISCV::C_ADDIW: {
284-
int64_t Offset = Inst.getOperand(2).getImm();
285-
if (Offset == 0)
286-
break;
287-
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
288-
uint64_t Mask = ~((uint64_t)0) >> 32;
289-
Target &= Mask;
290-
Target = *TargetRegState + SignExtend64<6>(Offset);
291-
Target = SignExtend64<32>(Target);
292-
return true;
293-
}
294-
break;
246+
default:
247+
return false;
248+
case RISCV::C_ADDI:
249+
case RISCV::ADDI: {
250+
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
251+
Target = *TargetRegState + Inst.getOperand(2).getImm();
252+
Target &= maskTrailingOnes<uint64_t>(ArchRegWidth);
253+
return true;
295254
}
296-
case RISCV::LB:
297-
case RISCV::LH:
298-
case RISCV::LD:
299-
case RISCV::LW:
300-
case RISCV::LBU:
301-
case RISCV::LHU:
302-
case RISCV::LWU:
303-
case RISCV::SB:
304-
case RISCV::SH:
305-
case RISCV::SW:
306-
case RISCV::SD:
307-
case RISCV::FLH:
308-
case RISCV::FLW:
309-
case RISCV::FLD:
310-
case RISCV::FSH:
311-
case RISCV::FSW:
312-
case RISCV::FSD: {
313-
int64_t Offset = SignExtend64<12>(Inst.getOperand(2).getImm());
314-
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg()))
315-
Target = *TargetRegState + Offset;
316-
else
317-
Target = Offset;
255+
break;
256+
}
257+
case RISCV::C_ADDIW:
258+
case RISCV::ADDIW: {
259+
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
260+
Target = *TargetRegState + Inst.getOperand(2).getImm();
261+
Target = SignExtend64<32>(Target);
318262
return true;
319263
}
320-
case RISCV::C_LD:
321-
case RISCV::C_SD:
322-
case RISCV::C_FLD:
323-
case RISCV::C_FSD:
324-
case RISCV::C_SW:
325-
case RISCV::C_LW:
326-
case RISCV::C_FSW:
327-
case RISCV::C_FLW: {
328-
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
329-
Target = *TargetRegState + Inst.getOperand(2).getImm();
330-
return true;
331-
}
332-
break;
264+
break;
265+
}
266+
case RISCV::LB:
267+
case RISCV::LH:
268+
case RISCV::LD:
269+
case RISCV::LW:
270+
case RISCV::LBU:
271+
case RISCV::LHU:
272+
case RISCV::LWU:
273+
case RISCV::SB:
274+
case RISCV::SH:
275+
case RISCV::SW:
276+
case RISCV::SD:
277+
case RISCV::FLH:
278+
case RISCV::FLW:
279+
case RISCV::FLD:
280+
case RISCV::FSH:
281+
case RISCV::FSW:
282+
case RISCV::FSD:
283+
case RISCV::C_LD:
284+
case RISCV::C_SD:
285+
case RISCV::C_FLD:
286+
case RISCV::C_FSD:
287+
case RISCV::C_SW:
288+
case RISCV::C_LW:
289+
case RISCV::C_FSW:
290+
case RISCV::C_FLW: {
291+
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
292+
Target = *TargetRegState + Inst.getOperand(2).getImm();
293+
return true;
333294
}
295+
break;
296+
}
334297
}
335298
return false;
336299
}
@@ -428,8 +391,12 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
428391

429392
} // end anonymous namespace
430393

431-
static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
432-
return new RISCVMCInstrAnalysis(Info);
394+
static MCInstrAnalysis *createRISCV32InstrAnalysis(const MCInstrInfo *Info) {
395+
return new RISCVMCInstrAnalysis(Info, 32);
396+
}
397+
398+
static MCInstrAnalysis *createRISCV64InstrAnalysis(const MCInstrInfo *Info) {
399+
return new RISCVMCInstrAnalysis(Info, 64);
433400
}
434401

435402
namespace {
@@ -455,12 +422,12 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
455422
TargetRegistry::RegisterELFStreamer(*T, createRISCVELFStreamer);
456423
TargetRegistry::RegisterObjectTargetStreamer(
457424
*T, createRISCVObjectTargetStreamer);
458-
TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
459-
460425
// Register the asm target streamer.
461426
TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
462427
// Register the null target streamer.
463428
TargetRegistry::RegisterNullTargetStreamer(*T,
464429
createRISCVNullTargetStreamer);
465430
}
431+
TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV32Target(), createRISCV32InstrAnalysis);
432+
TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV64Target(), createRISCV64InstrAnalysis);
466433
}

‎llvm/tools/llvm-objdump/llvm-objdump.cpp‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2323,9 +2323,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
23232323
if (Disassembled && DT->InstrAnalysis) {
23242324
llvm::raw_ostream *TargetOS = &FOS;
23252325
uint64_t Target;
2326-
int TargetArchBitWidth = DT->SubtargetInfo->getTargetTriple().getArchPointerBitWidth();
23272326
bool PrintTarget = DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index, Size, Target) ||
2328-
DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target, TargetArchBitWidth);
2327+
DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target, TargetOS);
23292328
if (!PrintTarget) {
23302329
if (std::optional<uint64_t> MaybeTarget =
23312330
DT->InstrAnalysis->evaluateMemoryOperandAddress(
@@ -2361,9 +2360,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
23612360
[=](const std::pair<uint64_t, SectionRef> &O) {
23622361
return O.first <= Target;
23632362
});
2364-
uint64_t TargetSecAddr = It == SectionAddresses.end() ? It->first : 0;
2363+
uint64_t TargetSecAddr = It == SectionAddresses.end() ? 0 : It->first;
23652364
bool FoundSymbols = false;
2366-
// missing case where begin == end as in this case, we are to return 0
23672365
while (It != SectionAddresses.begin()) {
23682366
--It;
23692367
if (It->first != TargetSecAddr) {
@@ -2491,7 +2489,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
24912489
<< ">";
24922490
} else if (LabelAvailable) {
24932491
*TargetOS << " <" << AllLabels[Target] << ">";
2494-
}
2492+
}
24952493
// By convention, each record in the comment stream should be
24962494
// terminated.
24972495
if (TargetOS == &CommentStream)

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