update test comment

paulwalker-arm · paulwalker-arm · commit e58bd1309870 · 2025-05-13T16:46:54.000Z
diff --git a/llvm/test/CodeGen/AArch64/sve2-bsl.ll b/llvm/test/CodeGen/AArch64/sve2-bsl.ll
@@ -300,7 +300,7 @@ define <vscale x 2 x i64> @codegen_bsl2n_i64(<vscale x 2 x i64> %0, <vscale x 2
   ret <vscale x 2 x i64> %7
 }
 
-; (A ^ B) & C) ^ B -> (A & C) ^ (B & !C) when BIC instructions are available.
+; (A ^ B) & C) ^ B -> (A & C) | (B & !C) when BIC instructions are available.
 define <vscale x 4 x i32> @bsl_combine_when_bic_available(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
 ; CHECK-LABEL: bsl_combine_when_bic_available:
 ; CHECK:       // %bb.0: // %entry

Original file line number	Diff line number	Diff line change
`@@ -300,7 +300,7 @@ define <vscale x 2 x i64> @codegen_bsl2n_i64(<vscale x 2 x i64> %0, <vscale x 2`
`300`	`300`	`ret <vscale x 2 x i64> %7`
`301`	`301`	`}`
`302`	`302`
`303`		`-; (A ^ B) & C) ^ B -> (A & C) ^ (B & !C) when BIC instructions are available.`
	`303`	`+; (A ^ B) & C) ^ B -> (A & C) \| (B & !C) when BIC instructions are available.`
`304`	`304`	`define <vscale x 4 x i32> @bsl_combine_when_bic_available(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {`
`305`	`305`	`; CHECK-LABEL: bsl_combine_when_bic_available:`
`306`	`306`	`; CHECK: // %bb.0: // %entry`