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[NFC][PowerPC] Cleanup isImm and getImmEncoding functions (#161567)
Refactor and replace explicit Imm `getImm*Encodng() | isU*Imm() | isS*Imm()` functions to a generic one that takes a template. This is in prep for followup batch to implement `paddis` which takes a pcrel Imm == 32bits. Doing this refactor so we don't have to copy and paste the same set of functions again with only the bit length changes.
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‎llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp‎

Lines changed: 21 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -349,32 +349,30 @@ struct PPCOperand : public MCParsedAsmOperand {
349349
bool isImm() const override {
350350
return Kind == Immediate || Kind == Expression;
351351
}
352-
bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
353-
bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
354-
bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
355-
bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
356-
bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
357-
bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
358-
bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
359-
bool isU6ImmX2() const { return Kind == Immediate &&
360-
isUInt<6>(getImm()) &&
361-
(getImm() & 1) == 0; }
362-
bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
363-
bool isU7ImmX4() const { return Kind == Immediate &&
364-
isUInt<7>(getImm()) &&
365-
(getImm() & 3) == 0; }
366-
bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
367-
bool isU8ImmX8() const { return Kind == Immediate &&
368-
isUInt<8>(getImm()) &&
369-
(getImm() & 7) == 0; }
370-
371-
bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
372-
bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
352+
353+
template <uint64_t N> bool isUImm() const {
354+
return Kind == Immediate && isUInt<N>(getImm());
355+
}
356+
template <uint64_t N> bool isSImm() const {
357+
return Kind == Immediate && isInt<N>(getImm());
358+
}
359+
bool isU6ImmX2() const { return isUImm<6>() && (getImm() & 1) == 0; }
360+
bool isU7ImmX4() const { return isUImm<7>() && (getImm() & 3) == 0; }
361+
bool isU8ImmX8() const { return isUImm<8>() && (getImm() & 7) == 0; }
362+
373363
bool isU16Imm() const { return isExtImm<16>(/*Signed*/ false, 1); }
374364
bool isS16Imm() const { return isExtImm<16>(/*Signed*/ true, 1); }
375365
bool isS16ImmX4() const { return isExtImm<16>(/*Signed*/ true, 4); }
376366
bool isS16ImmX16() const { return isExtImm<16>(/*Signed*/ true, 16); }
377367
bool isS17Imm() const { return isExtImm<17>(/*Signed*/ true, 1); }
368+
bool isS34Imm() const {
369+
// Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
370+
// ContextImmediate is needed.
371+
return Kind == Expression || isSImm<34>();
372+
}
373+
bool isS34ImmX16() const {
374+
return Kind == Expression || (isSImm<34>() && (getImm() & 15) == 0);
375+
}
378376

379377
bool isHashImmX8() const {
380378
// The Hash Imm form is used for instructions that check or store a hash.
@@ -384,16 +382,6 @@ struct PPCOperand : public MCParsedAsmOperand {
384382
(getImm() & 7) == 0);
385383
}
386384

387-
bool isS34ImmX16() const {
388-
return Kind == Expression ||
389-
(Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0);
390-
}
391-
bool isS34Imm() const {
392-
// Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
393-
// ContextImmediate is needed.
394-
return Kind == Expression || (Kind == Immediate && isInt<34>(getImm()));
395-
}
396-
397385
bool isTLSReg() const { return Kind == TLSRegister; }
398386
bool isDirectBr() const {
399387
if (Kind == Expression)
@@ -1637,7 +1625,7 @@ bool PPCAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
16371625
if (Operands.size() != 5)
16381626
return false;
16391627
PPCOperand &EHOp = (PPCOperand &)*Operands[4];
1640-
if (EHOp.isU1Imm() && EHOp.getImm() == 0)
1628+
if (EHOp.isUImm<1>() && EHOp.getImm() == 0)
16411629
Operands.pop_back();
16421630
}
16431631

@@ -1817,7 +1805,7 @@ unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
18171805
}
18181806

18191807
PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1820-
if (Op.isU3Imm() && Op.getImm() == ImmVal)
1808+
if (Op.isUImm<3>() && Op.getImm() == ImmVal)
18211809
return Match_Success;
18221810

18231811
return Match_InvalidOperand;

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp‎

Lines changed: 9 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -206,45 +206,24 @@ PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,
206206
return RegBits;
207207
}
208208

209-
unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
210-
SmallVectorImpl<MCFixup> &Fixups,
211-
const MCSubtargetInfo &STI) const {
212-
const MCOperand &MO = MI.getOperand(OpNo);
213-
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
214-
215-
// Add a fixup for the immediate field.
216-
addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(), PPC::fixup_ppc_half16);
217-
return 0;
218-
}
219-
220-
uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
221-
SmallVectorImpl<MCFixup> &Fixups,
222-
const MCSubtargetInfo &STI,
223-
MCFixupKind Fixup) const {
209+
template <MCFixupKind Fixup>
210+
uint64_t PPCMCCodeEmitter::getImmEncoding(const MCInst &MI, unsigned OpNo,
211+
SmallVectorImpl<MCFixup> &Fixups,
212+
const MCSubtargetInfo &STI) const {
224213
const MCOperand &MO = MI.getOperand(OpNo);
225214
assert(!MO.isReg() && "Not expecting a register for this operand.");
226215
if (MO.isImm())
227216
return getMachineOpValue(MI, MO, Fixups, STI);
228217

218+
uint32_t Offset = 0;
219+
if (Fixup == PPC::fixup_ppc_half16)
220+
Offset = IsLittleEndian ? 0 : 2;
221+
229222
// Add a fixup for the immediate field.
230-
addFixup(Fixups, 0, MO.getExpr(), Fixup);
223+
addFixup(Fixups, Offset, MO.getExpr(), Fixup);
231224
return 0;
232225
}
233226

234-
uint64_t
235-
PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
236-
SmallVectorImpl<MCFixup> &Fixups,
237-
const MCSubtargetInfo &STI) const {
238-
return getImm34Encoding(MI, OpNo, Fixups, STI, PPC::fixup_ppc_imm34);
239-
}
240-
241-
uint64_t
242-
PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
243-
SmallVectorImpl<MCFixup> &Fixups,
244-
const MCSubtargetInfo &STI) const {
245-
return getImm34Encoding(MI, OpNo, Fixups, STI, PPC::fixup_ppc_pcrel34);
246-
}
247-
248227
unsigned PPCMCCodeEmitter::getDispRIEncoding(const MCInst &MI, unsigned OpNo,
249228
SmallVectorImpl<MCFixup> &Fixups,
250229
const MCSubtargetInfo &STI) const {

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h‎

Lines changed: 4 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -47,19 +47,10 @@ class PPCMCCodeEmitter : public MCCodeEmitter {
4747
unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
4848
SmallVectorImpl<MCFixup> &Fixups,
4949
const MCSubtargetInfo &STI) const;
50-
unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
51-
SmallVectorImpl<MCFixup> &Fixups,
52-
const MCSubtargetInfo &STI) const;
53-
uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo,
54-
SmallVectorImpl<MCFixup> &Fixups,
55-
const MCSubtargetInfo &STI,
56-
MCFixupKind Fixup) const;
57-
uint64_t getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
58-
SmallVectorImpl<MCFixup> &Fixups,
59-
const MCSubtargetInfo &STI) const;
60-
uint64_t getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
61-
SmallVectorImpl<MCFixup> &Fixups,
62-
const MCSubtargetInfo &STI) const;
50+
template <MCFixupKind Fixup>
51+
uint64_t getImmEncoding(const MCInst &MI, unsigned OpNo,
52+
SmallVectorImpl<MCFixup> &Fixups,
53+
const MCSubtargetInfo &STI) const;
6354
unsigned getDispRIEncoding(const MCInst &MI, unsigned OpNo,
6455
SmallVectorImpl<MCFixup> &Fixups,
6556
const MCSubtargetInfo &STI) const;

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td‎

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -14,30 +14,6 @@
1414
//===----------------------------------------------------------------------===//
1515
// 64-bit operands.
1616
//
17-
def s16imm64 : Operand<i64> {
18-
let PrintMethod = "printS16ImmOperand";
19-
let EncoderMethod = "getImm16Encoding";
20-
let ParserMatchClass = PPCS16ImmAsmOperand;
21-
let DecoderMethod = "decodeSImmOperand<16>";
22-
let OperandType = "OPERAND_IMMEDIATE";
23-
}
24-
def u16imm64 : Operand<i64> {
25-
let PrintMethod = "printU16ImmOperand";
26-
let EncoderMethod = "getImm16Encoding";
27-
let ParserMatchClass = PPCU16ImmAsmOperand;
28-
let DecoderMethod = "decodeUImmOperand<16>";
29-
let OperandType = "OPERAND_IMMEDIATE";
30-
}
31-
def s17imm64 : Operand<i64> {
32-
// This operand type is used for addis/lis to allow the assembler parser
33-
// to accept immediates in the range -65536..65535 for compatibility with
34-
// the GNU assembler. The operand is treated as 16-bit otherwise.
35-
let PrintMethod = "printS16ImmOperand";
36-
let EncoderMethod = "getImm16Encoding";
37-
let ParserMatchClass = PPCS17ImmAsmOperand;
38-
let DecoderMethod = "decodeSImmOperand<16>";
39-
let OperandType = "OPERAND_IMMEDIATE";
40-
}
4117
def tocentry : Operand<iPTR> {
4218
let MIOperandInfo = (ops i64imm:$imm);
4319
}

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.td‎

Lines changed: 51 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -615,7 +615,8 @@ def spe4rc : RegisterOperand<GPRC> {
615615
}
616616

617617
def PPCU1ImmAsmOperand : AsmOperandClass {
618-
let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
618+
let Name = "U1Imm";
619+
let PredicateMethod = "isUImm<1>";
619620
let RenderMethod = "addImmOperands";
620621
}
621622
def u1imm : Operand<i32> {
@@ -626,7 +627,8 @@ def u1imm : Operand<i32> {
626627
}
627628

628629
def PPCU2ImmAsmOperand : AsmOperandClass {
629-
let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
630+
let Name = "U2Imm";
631+
let PredicateMethod = "isUImm<2>";
630632
let RenderMethod = "addImmOperands";
631633
}
632634
def u2imm : Operand<i32> {
@@ -647,7 +649,8 @@ def atimm : Operand<i32> {
647649
}
648650

649651
def PPCU3ImmAsmOperand : AsmOperandClass {
650-
let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
652+
let Name = "U3Imm";
653+
let PredicateMethod = "isUImm<3>";
651654
let RenderMethod = "addImmOperands";
652655
}
653656
def u3imm : Operand<i32> {
@@ -658,7 +661,8 @@ def u3imm : Operand<i32> {
658661
}
659662

660663
def PPCU4ImmAsmOperand : AsmOperandClass {
661-
let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
664+
let Name = "U4Imm";
665+
let PredicateMethod = "isUImm<4>";
662666
let RenderMethod = "addImmOperands";
663667
}
664668
def u4imm : Operand<i32> {
@@ -668,7 +672,8 @@ def u4imm : Operand<i32> {
668672
let OperandType = "OPERAND_IMMEDIATE";
669673
}
670674
def PPCS5ImmAsmOperand : AsmOperandClass {
671-
let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
675+
let Name = "S5Imm";
676+
let PredicateMethod = "isSImm<5>";
672677
let RenderMethod = "addImmOperands";
673678
}
674679
def s5imm : Operand<i32> {
@@ -678,7 +683,8 @@ def s5imm : Operand<i32> {
678683
let OperandType = "OPERAND_IMMEDIATE";
679684
}
680685
def PPCU5ImmAsmOperand : AsmOperandClass {
681-
let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
686+
let Name = "U5Imm";
687+
let PredicateMethod = "isUImm<5>";
682688
let RenderMethod = "addImmOperands";
683689
}
684690
def u5imm : Operand<i32> {
@@ -688,7 +694,8 @@ def u5imm : Operand<i32> {
688694
let OperandType = "OPERAND_IMMEDIATE";
689695
}
690696
def PPCU6ImmAsmOperand : AsmOperandClass {
691-
let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
697+
let Name = "U6Imm";
698+
let PredicateMethod = "isUImm<6>";
692699
let RenderMethod = "addImmOperands";
693700
}
694701
def u6imm : Operand<i32> {
@@ -698,7 +705,8 @@ def u6imm : Operand<i32> {
698705
let OperandType = "OPERAND_IMMEDIATE";
699706
}
700707
def PPCU7ImmAsmOperand : AsmOperandClass {
701-
let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
708+
let Name = "U7Imm";
709+
let PredicateMethod = "isUImm<7>";
702710
let RenderMethod = "addImmOperands";
703711
}
704712
def u7imm : Operand<i32> {
@@ -708,7 +716,8 @@ def u7imm : Operand<i32> {
708716
let OperandType = "OPERAND_IMMEDIATE";
709717
}
710718
def PPCU8ImmAsmOperand : AsmOperandClass {
711-
let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
719+
let Name = "U8Imm";
720+
let PredicateMethod = "isUImm<8>";
712721
let RenderMethod = "addImmOperands";
713722
}
714723
def u8imm : Operand<i32> {
@@ -718,7 +727,8 @@ def u8imm : Operand<i32> {
718727
let OperandType = "OPERAND_IMMEDIATE";
719728
}
720729
def PPCU10ImmAsmOperand : AsmOperandClass {
721-
let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
730+
let Name = "U10Imm";
731+
let PredicateMethod = "isUImm<10>";
722732
let RenderMethod = "addImmOperands";
723733
}
724734
def u10imm : Operand<i32> {
@@ -728,7 +738,8 @@ def u10imm : Operand<i32> {
728738
let OperandType = "OPERAND_IMMEDIATE";
729739
}
730740
def PPCU12ImmAsmOperand : AsmOperandClass {
731-
let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
741+
let Name = "U12Imm";
742+
let PredicateMethod = "isUImm<12>";
732743
let RenderMethod = "addImmOperands";
733744
}
734745
def u12imm : Operand<i32> {
@@ -743,7 +754,14 @@ def PPCS16ImmAsmOperand : AsmOperandClass {
743754
}
744755
def s16imm : Operand<i32> {
745756
let PrintMethod = "printS16ImmOperand";
746-
let EncoderMethod = "getImm16Encoding";
757+
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
758+
let ParserMatchClass = PPCS16ImmAsmOperand;
759+
let DecoderMethod = "decodeSImmOperand<16>";
760+
let OperandType = "OPERAND_IMMEDIATE";
761+
}
762+
def s16imm64 : Operand<i64> {
763+
let PrintMethod = "printS16ImmOperand";
764+
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
747765
let ParserMatchClass = PPCS16ImmAsmOperand;
748766
let DecoderMethod = "decodeSImmOperand<16>";
749767
let OperandType = "OPERAND_IMMEDIATE";
@@ -754,7 +772,14 @@ def PPCU16ImmAsmOperand : AsmOperandClass {
754772
}
755773
def u16imm : Operand<i32> {
756774
let PrintMethod = "printU16ImmOperand";
757-
let EncoderMethod = "getImm16Encoding";
775+
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
776+
let ParserMatchClass = PPCU16ImmAsmOperand;
777+
let DecoderMethod = "decodeUImmOperand<16>";
778+
let OperandType = "OPERAND_IMMEDIATE";
779+
}
780+
def u16imm64 : Operand<i64> {
781+
let PrintMethod = "printU16ImmOperand";
782+
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
758783
let ParserMatchClass = PPCU16ImmAsmOperand;
759784
let DecoderMethod = "decodeUImmOperand<16>";
760785
let OperandType = "OPERAND_IMMEDIATE";
@@ -768,7 +793,17 @@ def s17imm : Operand<i32> {
768793
// to accept immediates in the range -65536..65535 for compatibility with
769794
// the GNU assembler. The operand is treated as 16-bit otherwise.
770795
let PrintMethod = "printS16ImmOperand";
771-
let EncoderMethod = "getImm16Encoding";
796+
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
797+
let ParserMatchClass = PPCS17ImmAsmOperand;
798+
let DecoderMethod = "decodeSImmOperand<16>";
799+
let OperandType = "OPERAND_IMMEDIATE";
800+
}
801+
def s17imm64 : Operand<i64> {
802+
// This operand type is used for addis/lis to allow the assembler parser
803+
// to accept immediates in the range -65536..65535 for compatibility with
804+
// the GNU assembler. The operand is treated as 16-bit otherwise.
805+
let PrintMethod = "printS16ImmOperand";
806+
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
772807
let ParserMatchClass = PPCS17ImmAsmOperand;
773808
let DecoderMethod = "decodeSImmOperand<16>";
774809
let OperandType = "OPERAND_IMMEDIATE";
@@ -780,14 +815,14 @@ def PPCS34ImmAsmOperand : AsmOperandClass {
780815
}
781816
def s34imm : Operand<i64> {
782817
let PrintMethod = "printS34ImmOperand";
783-
let EncoderMethod = "getImm34EncodingNoPCRel";
818+
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_imm34>";
784819
let ParserMatchClass = PPCS34ImmAsmOperand;
785820
let DecoderMethod = "decodeSImmOperand<34>";
786821
let OperandType = "OPERAND_IMMEDIATE";
787822
}
788823
def s34imm_pcrel : Operand<i64> {
789824
let PrintMethod = "printS34ImmOperand";
790-
let EncoderMethod = "getImm34EncodingPCRel";
825+
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_pcrel34>";
791826
let ParserMatchClass = PPCS34ImmAsmOperand;
792827
let DecoderMethod = "decodeSImmOperand<34>";
793828
let OperandType = "OPERAND_IMMEDIATE";

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