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Add more tests to fprcvt-cvtf.ll
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‎llvm/test/CodeGen/AArch64/fprcvt-cvtf.ll‎

Lines changed: 158 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,23 @@ define half @scvtf_f16i32_neg(<4 x i32> %x) {
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ret half %conv
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}
4646

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define <1 x half> @scvtf_f16i32_simple(<1 x i32> %x) {
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; CHECK-LABEL: scvtf_f16i32_simple:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: scvtf h0, s0
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; CHECK-NEXT: ret
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;
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; CHECK-NO-FPRCVT-LABEL: scvtf_f16i32_simple:
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; CHECK-NO-FPRCVT: // %bb.0:
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; CHECK-NO-FPRCVT-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NO-FPRCVT-NEXT: scvtf s0, s0
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; CHECK-NO-FPRCVT-NEXT: fcvt h0, s0
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; CHECK-NO-FPRCVT-NEXT: ret
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%conv = sitofp <1 x i32> %x to <1 x half>
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ret <1 x half> %conv
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}
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4764
define double @scvtf_f64i32(<4 x i32> %x) {
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; CHECK-LABEL: scvtf_f64i32:
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; CHECK: // %bb.0:
@@ -77,6 +94,28 @@ define double @scvtf_f64i32_neg(<4 x i32> %x) {
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ret double %conv
7895
}
7996

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; This test does not give the indended result of scvtf d0, s0
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; This is due to the input being loaded as a 2 item vector and
99+
; therefore using vector inputs that do not match the pattern
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; This test will be fixed in a future revision
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define <1 x double> @scvtf_f64i32_simple(<1 x i32> %x) {
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; CHECK-LABEL: scvtf_f64i32_simple:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshll v0.2d, v0.2s, #0
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; CHECK-NEXT: scvtf v0.2d, v0.2d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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;
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; CHECK-NO-FPRCVT-LABEL: scvtf_f64i32_simple:
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; CHECK-NO-FPRCVT: // %bb.0:
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; CHECK-NO-FPRCVT-NEXT: sshll v0.2d, v0.2s, #0
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; CHECK-NO-FPRCVT-NEXT: scvtf v0.2d, v0.2d
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; CHECK-NO-FPRCVT-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NO-FPRCVT-NEXT: ret
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%conv = sitofp <1 x i32> %x to <1 x double>
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ret <1 x double> %conv
117+
}
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80119
define half @scvtf_f16i64(<2 x i64> %x) {
81120
; CHECK-LABEL: scvtf_f16i64:
82121
; CHECK: // %bb.0:
@@ -112,6 +151,24 @@ define half @scvtf_f16i64_neg(<2 x i64> %x) {
112151
ret half %conv
113152
}
114153

154+
define <1 x half> @scvtf_f16i64_simple(<1 x i64> %x) {
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; CHECK-LABEL: scvtf_f16i64_simple:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: scvtf h0, d0
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; CHECK-NEXT: ret
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;
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; CHECK-NO-FPRCVT-LABEL: scvtf_f16i64_simple:
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; CHECK-NO-FPRCVT: // %bb.0:
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; CHECK-NO-FPRCVT-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NO-FPRCVT-NEXT: fmov x8, d0
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; CHECK-NO-FPRCVT-NEXT: scvtf s0, x8
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; CHECK-NO-FPRCVT-NEXT: fcvt h0, s0
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; CHECK-NO-FPRCVT-NEXT: ret
168+
%conv = sitofp <1 x i64> %x to <1 x half>
169+
ret <1 x half> %conv
170+
}
171+
115172
define float @scvtf_f32i64(<2 x i64> %x) {
116173
; CHECK-LABEL: scvtf_f32i64:
117174
; CHECK: // %bb.0:
@@ -145,6 +202,28 @@ define float @scvtf_f32i64_neg(<2 x i64> %x) {
145202
ret float %conv
146203
}
147204

205+
; This test does not give the indended result of scvtf s0, d0
206+
; This is due to the input being loaded as a 2 item vector and
207+
; therefore using vector inputs that do not match the pattern
208+
; This test will be fixed in a future revision
209+
define <1 x float> @scvtf_f32i64_simple(<1 x i64> %x) {
210+
; CHECK-LABEL: scvtf_f32i64_simple:
211+
; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: scvtf v0.2d, v0.2d
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; CHECK-NEXT: fcvtn v0.2s, v0.2d
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; CHECK-NEXT: ret
216+
;
217+
; CHECK-NO-FPRCVT-LABEL: scvtf_f32i64_simple:
218+
; CHECK-NO-FPRCVT: // %bb.0:
219+
; CHECK-NO-FPRCVT-NEXT: // kill: def $d0 killed $d0 def $q0
220+
; CHECK-NO-FPRCVT-NEXT: scvtf v0.2d, v0.2d
221+
; CHECK-NO-FPRCVT-NEXT: fcvtn v0.2s, v0.2d
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; CHECK-NO-FPRCVT-NEXT: ret
223+
%conv = sitofp <1 x i64> %x to <1 x float>
224+
ret <1 x float> %conv
225+
}
226+
148227
; UCVTF
149228

150229
define half @ucvtf_f16i32(<4 x i32> %x) {
@@ -181,6 +260,23 @@ define half @ucvtf_f16i32_neg(<4 x i32> %x) {
181260
ret half %conv
182261
}
183262

263+
define <1 x half> @ucvtf_f16i32_simple(<1 x i32> %x) {
264+
; CHECK-LABEL: ucvtf_f16i32_simple:
265+
; CHECK: // %bb.0:
266+
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
267+
; CHECK-NEXT: ucvtf h0, s0
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; CHECK-NEXT: ret
269+
;
270+
; CHECK-NO-FPRCVT-LABEL: ucvtf_f16i32_simple:
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; CHECK-NO-FPRCVT: // %bb.0:
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; CHECK-NO-FPRCVT-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NO-FPRCVT-NEXT: ucvtf s0, s0
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; CHECK-NO-FPRCVT-NEXT: fcvt h0, s0
275+
; CHECK-NO-FPRCVT-NEXT: ret
276+
%conv = uitofp <1 x i32> %x to <1 x half>
277+
ret <1 x half> %conv
278+
}
279+
184280
define double @ucvtf_f64i32(<4 x i32> %x) {
185281
; CHECK-LABEL: ucvtf_f64i32:
186282
; CHECK: // %bb.0:
@@ -214,6 +310,28 @@ define double @ucvtf_f64i32_neg(<4 x i32> %x) {
214310
ret double %conv
215311
}
216312

313+
; This test does not give the indended result of ucvtf d0, s0
314+
; This is due to the input being loaded as a 2 item vector and
315+
; therefore using vector inputs that do not match the pattern
316+
; This test will be fixed in a future revision
317+
define <1 x double> @ucvtf_f64i32_simple(<1 x i32> %x) {
318+
; CHECK-LABEL: ucvtf_f64i32_simple:
319+
; CHECK: // %bb.0:
320+
; CHECK-NEXT: ushll v0.2d, v0.2s, #0
321+
; CHECK-NEXT: ucvtf v0.2d, v0.2d
322+
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
323+
; CHECK-NEXT: ret
324+
;
325+
; CHECK-NO-FPRCVT-LABEL: ucvtf_f64i32_simple:
326+
; CHECK-NO-FPRCVT: // %bb.0:
327+
; CHECK-NO-FPRCVT-NEXT: ushll v0.2d, v0.2s, #0
328+
; CHECK-NO-FPRCVT-NEXT: ucvtf v0.2d, v0.2d
329+
; CHECK-NO-FPRCVT-NEXT: // kill: def $d0 killed $d0 killed $q0
330+
; CHECK-NO-FPRCVT-NEXT: ret
331+
%conv = uitofp <1 x i32> %x to <1 x double>
332+
ret <1 x double> %conv
333+
}
334+
217335
define half @ucvtf_f16i64(<2 x i64> %x) {
218336
; CHECK-LABEL: ucvtf_f16i64:
219337
; CHECK: // %bb.0:
@@ -249,6 +367,24 @@ define half @ucvtf_f16i64_neg(<2 x i64> %x) {
249367
ret half %conv
250368
}
251369

370+
define <1 x half> @ucvtf_f16i64_simple(<1 x i64> %x) {
371+
; CHECK-LABEL: ucvtf_f16i64_simple:
372+
; CHECK: // %bb.0:
373+
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
374+
; CHECK-NEXT: ucvtf h0, d0
375+
; CHECK-NEXT: ret
376+
;
377+
; CHECK-NO-FPRCVT-LABEL: ucvtf_f16i64_simple:
378+
; CHECK-NO-FPRCVT: // %bb.0:
379+
; CHECK-NO-FPRCVT-NEXT: // kill: def $d0 killed $d0 def $q0
380+
; CHECK-NO-FPRCVT-NEXT: fmov x8, d0
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; CHECK-NO-FPRCVT-NEXT: ucvtf s0, x8
382+
; CHECK-NO-FPRCVT-NEXT: fcvt h0, s0
383+
; CHECK-NO-FPRCVT-NEXT: ret
384+
%conv = uitofp <1 x i64> %x to <1 x half>
385+
ret <1 x half> %conv
386+
}
387+
252388
define float @ucvtf_f32i64(<2 x i64> %x) {
253389
; CHECK-LABEL: ucvtf_f32i64:
254390
; CHECK: // %bb.0:
@@ -281,3 +417,25 @@ define float @ucvtf_f32i64_neg(<2 x i64> %x) {
281417
%conv = uitofp i64 %extract to float
282418
ret float %conv
283419
}
420+
421+
; This test does not give the indended result of ucvtf s0, d0
422+
; This is due to the input being loaded as a 2 item vector and
423+
; therefore using vector inputs that do not match the pattern
424+
; This test will be fixed in a future revision
425+
define <1 x float> @ucvtf_f32i64_simple(<1 x i64> %x) {
426+
; CHECK-LABEL: ucvtf_f32i64_simple:
427+
; CHECK: // %bb.0:
428+
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
429+
; CHECK-NEXT: ucvtf v0.2d, v0.2d
430+
; CHECK-NEXT: fcvtn v0.2s, v0.2d
431+
; CHECK-NEXT: ret
432+
;
433+
; CHECK-NO-FPRCVT-LABEL: ucvtf_f32i64_simple:
434+
; CHECK-NO-FPRCVT: // %bb.0:
435+
; CHECK-NO-FPRCVT-NEXT: // kill: def $d0 killed $d0 def $q0
436+
; CHECK-NO-FPRCVT-NEXT: ucvtf v0.2d, v0.2d
437+
; CHECK-NO-FPRCVT-NEXT: fcvtn v0.2s, v0.2d
438+
; CHECK-NO-FPRCVT-NEXT: ret
439+
%conv = uitofp <1 x i64> %x to <1 x float>
440+
ret <1 x float> %conv
441+
}

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