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[RISCV] Simplify Zcf/Zce/Zcd Predicates
This is a big change, trying to simplify our instruction predicates against the instruction spec. The overall approach is this: - Trust RISCVISAInfo to expand Zce/C with F and Zce/Z with D correctly adding `Zcd` and `Zcf`. This will be done by clang. Add more coverage for checking the C+F/C+D combinations specifically. - Simplify the predicates to stop checking if `Subtarget->HasStdExtC()` and `Subtarget->hasStdExtZce()`, trusting the enabled-ness of Zcf/Zcd. - Remove llc/llvm-mc test lines that assume `+c,+f` will be equivalent to `+zcf` (and equivalently for `+zcd`). - Simplify lots of error messages to only point at Zcf/Zcd. - Deprecate the accessors in RISCVSubtarget, for their generated equivalents. There is one breaking change: `.option arch, +zce, +f` no longer enables the Zcf instructions, because don't expand all the implications of extensions in this assembly directive.
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-187
lines changed

16 files changed

+136
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lines changed

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 8 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -404,18 +404,20 @@ def FeatureStdExtZcd
404404
"Compressed Double-Precision Floating-Point Instructions",
405405
[FeatureStdExtD, FeatureStdExtZca]>,
406406
RISCVExtensionBitmask<1, 4>;
407-
408-
def HasStdExtCOrZcd
409-
: Predicate<"Subtarget->hasStdExtCOrZcd()">,
410-
AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
411-
"'C' (Compressed Instructions) or "
407+
def HasStdExtZcd
408+
: Predicate<"Subtarget->hasStdExtZcd()">,
409+
AssemblerPredicate<(any_of FeatureStdExtZcd),
412410
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
413411

414412
def FeatureStdExtZcf
415413
: RISCVExtension<1, 0,
416414
"Compressed Single-Precision Floating-Point Instructions",
417415
[FeatureStdExtF, FeatureStdExtZca]>,
418416
RISCVExtensionBitmask<1, 5>;
417+
def HasStdExtZcf
418+
: Predicate<"Subtarget->hasStdExtZcf()">,
419+
AssemblerPredicate<(any_of FeatureStdExtZcf),
420+
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
419421

420422
def FeatureStdExtZclsd
421423
: RISCVExtension<1, 0,
@@ -431,7 +433,7 @@ def FeatureStdExtZcmp
431433
"sequenced instructions for code-size reduction",
432434
[FeatureStdExtZca]>,
433435
RISCVExtensionBitmask<1, 10>;
434-
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
436+
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp()">,
435437
AssemblerPredicate<(all_of FeatureStdExtZcmp),
436438
"'Zcmp' (sequenced instructions for code-size reduction)">;
437439

@@ -449,14 +451,6 @@ def FeatureStdExtZce
449451
[FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
450452
FeatureStdExtZcmt]>;
451453

452-
def HasStdExtCOrZcfOrZce
453-
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() ||"
454-
"Subtarget->hasStdExtZce()">,
455-
AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
456-
FeatureStdExtZce),
457-
"'C' (Compressed Instructions) or "
458-
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
459-
460454
def FeatureStdExtZcmop
461455
: RISCVExtension<1, 0, "Compressed May-Be-Operations",
462456
[FeatureStdExtZca]>,

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -301,7 +301,7 @@ def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
301301
let Inst{5} = imm{3};
302302
}
303303

304-
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
304+
let Predicates = [HasStdExtZcd, HasStdExtD] in
305305
def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>,
306306
Sched<[WriteFLD64, ReadFMemBase]> {
307307
bits<8> imm;
@@ -327,7 +327,7 @@ def C_LW_INX : CLoad_ri<0b010, "c.lw", GPRF32C, uimm7_lsb00>,
327327
}
328328

329329
let DecoderNamespace = "RV32Only",
330-
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
330+
Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
331331
def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
332332
Sched<[WriteFLD32, ReadFMemBase]> {
333333
bits<7> imm;
@@ -344,7 +344,7 @@ def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
344344
let Inst{6-5} = imm{7-6};
345345
}
346346

347-
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
347+
let Predicates = [HasStdExtZcd, HasStdExtD] in
348348
def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>,
349349
Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
350350
bits<8> imm;
@@ -370,7 +370,7 @@ def C_SW_INX : CStore_rri<0b110, "c.sw", GPRF32C, uimm7_lsb00>,
370370
}
371371

372372
let DecoderNamespace = "RV32Only",
373-
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
373+
Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
374374
def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
375375
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
376376
bits<7> imm;
@@ -500,7 +500,7 @@ def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb),
500500
let Constraints = "$rd = $rd_wb";
501501
}
502502

503-
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
503+
let Predicates = [HasStdExtZcd, HasStdExtD] in
504504
def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
505505
Sched<[WriteFLD64, ReadFMemBase]> {
506506
let Inst{4-2} = imm{8-6};
@@ -518,7 +518,7 @@ def C_LWSP_INX : CStackLoad<0b010, "c.lwsp", GPRF32NoX0, uimm8_lsb00>,
518518
}
519519

520520
let DecoderNamespace = "RV32Only",
521-
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
521+
Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
522522
def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
523523
Sched<[WriteFLD32, ReadFMemBase]> {
524524
let Inst{3-2} = imm{7-6};
@@ -560,7 +560,7 @@ def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPR:$rd),
560560
let Constraints = "$rs1 = $rd";
561561
}
562562

563-
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
563+
let Predicates = [HasStdExtZcd, HasStdExtD] in
564564
def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
565565
Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
566566
let Inst{9-7} = imm{8-6};
@@ -578,7 +578,7 @@ def C_SWSP_INX : CStackStore<0b110, "c.swsp", GPRF32, uimm8_lsb00>,
578578
}
579579

580580
let DecoderNamespace = "RV32Only",
581-
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
581+
Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
582582
def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
583583
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
584584
let Inst{8-7} = imm{7-6};
@@ -648,14 +648,14 @@ def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRNoX0:$rd, SPMem:$rs1, 0)>;
648648
def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPR:$rs2, SPMem:$rs1, 0)>;
649649
}
650650

651-
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
651+
let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
652652
def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRCMem:$rs1, 0)>;
653653
def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRCMem:$rs1, 0)>;
654654
def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32:$rd, SPMem:$rs1, 0)>;
655655
def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32:$rs2, SPMem:$rs1, 0)>;
656656
}
657657

658-
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
658+
let Predicates = [HasStdExtZcd, HasStdExtD] in {
659659
def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRCMem:$rs1, 0)>;
660660
def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRCMem:$rs1, 0)>;
661661
def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64:$rd, SPMem:$rs1, 0)>;
@@ -776,10 +776,10 @@ def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
776776
(C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>;
777777
} // Predicates = [HasStdExtZca]
778778

779-
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
779+
let Predicates = [HasStdExtZcd, HasStdExtD] in {
780780
def : CompressPat<(FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
781781
(C_FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
782-
} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
782+
} // Predicates = [HasStdExtZcd, HasStdExtD]
783783

784784
let Predicates = [HasStdExtZca] in {
785785
def : CompressPat<(LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
@@ -790,20 +790,20 @@ def : CompressPat<(LW_INX GPRF32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
790790
(C_LW_INX GPRF32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
791791
} // Predicates = [HasStdExtZca]
792792

793-
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
793+
let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
794794
def : CompressPat<(FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
795795
(C_FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
796-
} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
796+
} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
797797

798798
let Predicates = [HasStdExtZca, IsRV64] in {
799799
def : CompressPat<(LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
800800
(C_LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
801801
} // Predicates = [HasStdExtZca, IsRV64]
802802

803-
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
803+
let Predicates = [HasStdExtZcd, HasStdExtD] in {
804804
def : CompressPat<(FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),
805805
(C_FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
806-
} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
806+
} // Predicates = [HasStdExtZcd, HasStdExtD]
807807

808808
let Predicates = [HasStdExtZca] in {
809809
def : CompressPat<(SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
@@ -814,10 +814,10 @@ def : CompressPat<(SW_INX GPRF32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
814814
(C_SW_INX GPRF32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
815815
} // Predicates = [HasStdExtZca]
816816

817-
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
817+
let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
818818
def : CompressPat<(FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
819819
(C_FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
820-
} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
820+
} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
821821

822822
let Predicates = [HasStdExtZca, IsRV64] in {
823823
def : CompressPat<(SD GPRC:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),
@@ -907,10 +907,10 @@ def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
907907
(C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>;
908908
} // Predicates = [HasStdExtZca]
909909

910-
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
910+
let Predicates = [HasStdExtZcd, HasStdExtD] in {
911911
def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
912912
(C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
913-
} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
913+
} // Predicates = [HasStdExtZcd, HasStdExtD]
914914

915915
let Predicates = [HasStdExtZca] in {
916916
def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
@@ -921,10 +921,10 @@ def : CompressPat<(LW_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
921921
(C_LWSP_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
922922
} // Predicates = [HasStdExtZca]
923923

924-
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
924+
let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
925925
def : CompressPat<(FLW FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
926926
(C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
927-
} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
927+
} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
928928

929929
let Predicates = [HasStdExtZca, IsRV64] in {
930930
def : CompressPat<(LD GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
@@ -953,10 +953,10 @@ def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs1),
953953
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
954954
} // Predicates = [HasStdExtZca]
955955

956-
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
956+
let Predicates = [HasStdExtZcd, HasStdExtD] in {
957957
def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
958958
(C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
959-
} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
959+
} // Predicates = [HasStdExtZcd, HasStdExtD]
960960

961961
let Predicates = [HasStdExtZca] in {
962962
def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
@@ -967,10 +967,10 @@ def : CompressPat<(SW_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
967967
(C_SWSP_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
968968
} // Predicates = [HasStdExtZca]
969969

970-
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
970+
let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
971971
def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
972972
(C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
973-
} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
973+
} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
974974

975975
let Predicates = [HasStdExtZca, IsRV64] in {
976976
def : CompressPat<(SD GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),

‎llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -211,9 +211,9 @@ static bool isCompressibleLoad(const MachineInstr &MI) {
211211
case RISCV::LD_RV32:
212212
return STI.hasStdExtZclsd();
213213
case RISCV::FLW:
214-
return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce();
214+
return !STI.is64Bit() && STI.hasStdExtZcf();
215215
case RISCV::FLD:
216-
return STI.hasStdExtCOrZcd();
216+
return STI.hasStdExtZcd();
217217
}
218218
}
219219

@@ -235,9 +235,9 @@ static bool isCompressibleStore(const MachineInstr &MI) {
235235
case RISCV::SD_RV32:
236236
return STI.hasStdExtZclsd();
237237
case RISCV::FSW:
238-
return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce();
238+
return !STI.is64Bit() && STI.hasStdExtZcf();
239239
case RISCV::FSD:
240-
return STI.hasStdExtCOrZcd();
240+
return STI.hasStdExtZcd();
241241
}
242242
}
243243

‎llvm/lib/Target/RISCV/RISCVSubtarget.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,10 +171,15 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
171171

172172
LLVM_DEPRECATED("Now Equivalent to hasStdExtZca", "hasStdExtZca")
173173
bool hasStdExtCOrZca() const { return HasStdExtZca; }
174+
175+
LLVM_DEPRECATED("Equivalent to hasStdExtZcd", "hasStdExtZcd")
174176
bool hasStdExtCOrZcd() const { return HasStdExtC || HasStdExtZcd; }
177+
178+
LLVM_DEPRECATED("Equivalent to hasStdExtZcf", "hasStdExtZcf")
175179
bool hasStdExtCOrZcfOrZce() const {
176180
return HasStdExtC || HasStdExtZcf || HasStdExtZce;
177181
}
182+
178183
bool hasStdExtZvl() const { return ZvlLen != 0; }
179184
bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
180185
bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }

‎llvm/test/CodeGen/RISCV/compress-float.ll‎

Lines changed: 0 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -5,27 +5,6 @@
55
;
66
; RUN: cat %s > %t.tgtattr
77
; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
8-
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c,+f -filetype=obj \
9-
; RUN: -disable-block-placement < %t.tgtattr \
10-
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
11-
; RUN: | FileCheck -check-prefix=RV32IFDC %s
12-
;
13-
; RUN: cat %s > %t.fnattr
14-
; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f" }' >> %t.fnattr
15-
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
16-
; RUN: -disable-block-placement < %t.fnattr \
17-
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
18-
; RUN: | FileCheck -check-prefix=RV32IFDC %s
19-
;
20-
; RUN: cat %s > %t.mixedattr
21-
; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
22-
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c -filetype=obj \
23-
; RUN: -disable-block-placement < %t.mixedattr \
24-
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
25-
; RUN: | FileCheck -check-prefix=RV32IFDC %s
26-
;
27-
; RUN: cat %s > %t.tgtattr
28-
; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
298
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf,+f -filetype=obj \
309
; RUN: -disable-block-placement < %t.tgtattr \
3110
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
@@ -44,27 +23,6 @@
4423
; RUN: -disable-block-placement < %t.mixedattr \
4524
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
4625
; RUN: | FileCheck -check-prefix=RV32IFDC %s
47-
;
48-
; RUN: cat %s > %t.tgtattr
49-
; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
50-
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce,+f -filetype=obj \
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; RUN: -disable-block-placement < %t.tgtattr \
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; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IFDC %s
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;
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; RUN: cat %s > %t.fnattr
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; RUN: echo 'attributes #0 = { nounwind "target-features"="+zce,+f" }' >> %t.fnattr
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; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
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; RUN: -disable-block-placement < %t.fnattr \
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; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IFDC %s
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;
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; RUN: cat %s > %t.mixedattr
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; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
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; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce -filetype=obj \
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; RUN: -disable-block-placement < %t.mixedattr \
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; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IFDC %s
6826

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; This acts as a basic correctness check for the codegen instruction compression
7028
; path, verifying that the assembled file contains compressed instructions when

‎llvm/test/MC/RISCV/compress-rv32d.s‎

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# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding < %s \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
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# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding \
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# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
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# RUN: | llvm-objdump --no-print-imm-hex --triple=riscv32 --mattr=+c,+d -d - \
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# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
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# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
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# RUN: | llvm-objdump --no-print-imm-hex --triple=riscv32 --mattr=+c,+d -d -M no-aliases - \
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# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
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# RUN: llvm-mc -triple riscv32 -mattr=+zcd,+d -show-encoding < %s \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
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# RUN: llvm-mc -triple riscv32 -mattr=+zcd,+d -show-encoding \
@@ -19,16 +9,6 @@
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# RUN: | llvm-objdump --no-print-imm-hex --triple=riscv32 --mattr=+zcd,+d -d -M no-aliases - \
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# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
2111

22-
# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding < %s \
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# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
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# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding \
25-
# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
26-
# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
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# RUN: | llvm-objdump --no-print-imm-hex --triple=riscv64 --mattr=+c,+d -d - \
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# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
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# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
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# RUN: | llvm-objdump --no-print-imm-hex --triple=riscv64 --mattr=+c,+d -d -M no-aliases - \
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# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
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# RUN: llvm-mc -triple riscv64 -mattr=+zcd,+d -show-encoding < %s \
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# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
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# RUN: llvm-mc -triple riscv64 -mattr=+zcd,+d -show-encoding \

‎llvm/test/MC/RISCV/compress-rv32f.s‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
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# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding < %s \
2-
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
3-
# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding \
4-
# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
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# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+f --no-print-imm-hex -d - \
7-
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
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# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
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# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+f --no-print-imm-hex -d -M no-aliases - \
10-
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
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# RUN: llvm-mc -triple riscv32 -mattr=+zcf,+f -show-encoding < %s \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
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# RUN: llvm-mc -triple riscv32 -mattr=+zcf,+f -show-encoding \

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