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[IndVars,LV] Add tests for missed SCEV simplifications with muls.
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‎llvm/test/Transforms/IndVarSimplify/rewrite-loop-exit-values-phi.ll‎

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Original file line numberDiff line numberDiff line change
@@ -68,3 +68,44 @@ latch: ; preds = %inner_exit
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end: ; preds = %header
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ret void
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}
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declare void @foo()
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define i64 @narow_canonical_iv_wide_multiplied_iv(i32 %x, i64 %y, ptr %0) {
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; CHECK-LABEL: @narow_canonical_iv_wide_multiplied_iv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SMAX:%.*]] = tail call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 1)
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; CHECK-NEXT: [[MUL_Y:%.*]] = shl i64 [[Y:%.*]], 1
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_MUL:%.*]] = phi i64 [ 1, [[ENTRY]] ], [ [[IV_MUL_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_MUL_NEXT]] = add i64 [[IV_MUL]], [[MUL_Y]]
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; CHECK-NEXT: call void @foo()
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[EC:%.*]] = icmp ne i32 [[IV_NEXT]], [[SMAX]]
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; CHECK-NEXT: br i1 [[EC]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[TMP6:%.*]] = phi i64 [ [[IV_MUL_NEXT]], [[LOOP]] ]
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; CHECK-NEXT: ret i64 [[TMP6]]
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;
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entry:
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%smax = tail call i32 @llvm.smax.i32(i32 %x, i32 1)
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%mul.y = shl i64 %y, 1
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
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%iv.mul = phi i64 [ 1, %entry ], [ %iv.mul.next, %loop ]
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%iv.mul.next = add i64 %iv.mul, %mul.y
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call void @foo()
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%iv.next = add i32 %iv, 1
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%ec = icmp ult i32 %iv.next, %smax
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br i1 %ec, label %loop, label %exit
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exit:
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ret i64 %iv.mul.next
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}
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declare i32 @llvm.smax.i32(i32, i32)

‎llvm/test/Transforms/LoopVectorize/runtime-check.ll‎

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Original file line numberDiff line numberDiff line change
@@ -475,6 +475,107 @@ for.body:
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br i1 %exitcond, label %for.cond.cleanup, label %for.body, !llvm.loop !12
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}
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declare i1 @cond()
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define void @test_scev_check_mul_add_expansion(ptr %out, ptr %in, i32 %len, i32 %d) {
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; CHECK-LABEL: @test_scev_check_mul_add_expansion(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[PRE_1:%.*]] = icmp samesign ugt i32 [[D:%.*]], 5
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[PRE_1]])
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; CHECK-NEXT: [[PRE_2:%.*]] = icmp ult i32 [[D]], 7
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[PRE_2]])
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; CHECK-NEXT: [[PRE_3:%.*]] = icmp slt i32 [[D]], [[LEN:%.*]]
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[PRE_3]])
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; CHECK-NEXT: [[SMAX3:%.*]] = call i32 @llvm.smax.i32(i32 [[LEN]], i32 7)
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; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[SMAX3]], -6
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp slt i32 [[LEN]], 10
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]
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; CHECK: vector.memcheck:
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[OUT:%.*]], i64 12
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; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[LEN]], -7
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; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i64 [[TMP2]], 1
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[OUT]], i64 [[TMP3]]
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; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[TMP4]], i64 14
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; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[IN:%.*]], i64 4
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; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[SCEVGEP]], [[SCEVGEP2]]
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; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[IN]], [[SCEVGEP1]]
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; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
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; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[TMP0]], -4
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; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[N_VEC]], 6
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 [[INDEX]], 6
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; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[OFFSET_IDX]] to i64
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i16, ptr [[OUT]], i64 [[TMP6]]
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; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr [[TMP7]], align 2, !alias.scope [[META42:![0-9]+]], !noalias [[META45:![0-9]+]]
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; CHECK-NEXT: store i32 0, ptr [[IN]], align 4, !alias.scope [[META45]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP47:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP0]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP5]], [[MIDDLE_BLOCK]] ], [ 6, [[ENTRY:%.*]] ], [ 6, [[VECTOR_MEMCHECK]] ]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[TMP9:%.*]] = sext i32 [[IV]] to i64
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; CHECK-NEXT: [[ARRAYIDX80:%.*]] = getelementptr i16, ptr [[OUT]], i64 [[TMP9]]
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; CHECK-NEXT: store i16 0, ptr [[ARRAYIDX80]], align 2
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: store i32 0, ptr [[IN]], align 4
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; CHECK-NEXT: [[CMP7_NOT:%.*]] = icmp sgt i32 [[LEN]], [[IV_NEXT]]
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; CHECK-NEXT: br i1 [[CMP7_NOT]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP48:![0-9]+]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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; FORCED_OPTSIZE-LABEL: @test_scev_check_mul_add_expansion(
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; FORCED_OPTSIZE-NEXT: entry:
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; FORCED_OPTSIZE-NEXT: [[PRE_1:%.*]] = icmp sgt i32 [[D:%.*]], 5
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; FORCED_OPTSIZE-NEXT: tail call void @llvm.assume(i1 [[PRE_1]])
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; FORCED_OPTSIZE-NEXT: [[PRE_2:%.*]] = icmp samesign ule i32 [[D]], 6
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; FORCED_OPTSIZE-NEXT: tail call void @llvm.assume(i1 [[PRE_2]])
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; FORCED_OPTSIZE-NEXT: [[PRE_3:%.*]] = icmp slt i32 [[D]], [[LEN:%.*]]
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; FORCED_OPTSIZE-NEXT: tail call void @llvm.assume(i1 [[PRE_3]])
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; FORCED_OPTSIZE-NEXT: br label [[LOOP:%.*]]
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; FORCED_OPTSIZE: loop:
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; FORCED_OPTSIZE-NEXT: [[IV:%.*]] = phi i32 [ 6, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; FORCED_OPTSIZE-NEXT: [[ARRAYIDX80:%.*]] = getelementptr i16, ptr [[OUT:%.*]], i32 [[IV]]
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; FORCED_OPTSIZE-NEXT: store i16 0, ptr [[ARRAYIDX80]], align 2
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; FORCED_OPTSIZE-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; FORCED_OPTSIZE-NEXT: store i32 0, ptr [[IN:%.*]], align 4
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; FORCED_OPTSIZE-NEXT: [[CMP7_NOT:%.*]] = icmp sgt i32 [[LEN]], [[IV_NEXT]]
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; FORCED_OPTSIZE-NEXT: br i1 [[CMP7_NOT]], label [[LOOP]], label [[EXIT:%.*]]
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; FORCED_OPTSIZE: exit:
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; FORCED_OPTSIZE-NEXT: ret void
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;
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entry:
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%pre.1 = icmp sgt i32 %d, 5
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tail call void @llvm.assume(i1 %pre.1)
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%pre.2 = icmp samesign ule i32 %d, 6
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tail call void @llvm.assume(i1 %pre.2)
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%pre.3 = icmp slt i32 %d, %len
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tail call void @llvm.assume(i1 %pre.3)
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br label %loop
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loop:
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%iv = phi i32 [ 6, %entry ], [ %iv.next, %loop ]
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%arrayidx80 = getelementptr i16, ptr %out, i32 %iv
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store i16 0, ptr %arrayidx80, align 2
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%iv.next = add nuw nsw i32 %iv, 1
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store i32 0, ptr %in, align 4
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%cmp7.not = icmp sgt i32 %len, %iv.next
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br i1 %cmp7.not, label %loop, label %exit
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exit:
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ret void
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}
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; CHECK: !9 = !DILocation(line: 101, column: 1, scope: !{{.*}})
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!llvm.module.flags = !{!0, !1}

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