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[LV] Exercise type-mismatch with RT-check conflict rdx (#130295)
The test suite of LoopVectorize suffers from a coverage hole when types mismatch, and runtime checks are needed, with a conflict redux. Fix this coverage hole by adding tests.
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‎llvm/test/Transforms/LoopVectorize/runtime-check.ll

Lines changed: 111 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -300,6 +300,115 @@ loopexit:
300300
ret void
301301
}
302302

303+
define void @different_load_store_pairs(ptr %src.1, ptr %src.2, ptr %dst.1, ptr %dst.2, i64 %n) {
304+
; CHECK-LABEL: @different_load_store_pairs(
305+
; CHECK-NEXT: entry:
306+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX19:%.*]], 4
307+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]
308+
; CHECK: vector.memcheck:
309+
; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[UMAX19]], 2
310+
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST_1:%.*]], i64 [[TMP0]]
311+
; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[UMAX19]], 3
312+
; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[DST_2:%.*]], i64 [[TMP1]]
313+
; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SRC_1:%.*]], i64 [[TMP0]]
314+
; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[SRC_2:%.*]], i64 [[TMP1]]
315+
; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST_1]], [[SCEVGEP1]]
316+
; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[DST_2]], [[SCEVGEP]]
317+
; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
318+
; CHECK-NEXT: [[BOUND04:%.*]] = icmp ult ptr [[DST_1]], [[SCEVGEP2]]
319+
; CHECK-NEXT: [[BOUND15:%.*]] = icmp ult ptr [[SRC_1]], [[SCEVGEP]]
320+
; CHECK-NEXT: [[FOUND_CONFLICT6:%.*]] = and i1 [[BOUND04]], [[BOUND15]]
321+
; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT6]]
322+
; CHECK-NEXT: [[BOUND07:%.*]] = icmp ult ptr [[DST_1]], [[SCEVGEP3]]
323+
; CHECK-NEXT: [[BOUND18:%.*]] = icmp ult ptr [[SRC_2]], [[SCEVGEP]]
324+
; CHECK-NEXT: [[FOUND_CONFLICT9:%.*]] = and i1 [[BOUND07]], [[BOUND18]]
325+
; CHECK-NEXT: [[CONFLICT_RDX10:%.*]] = or i1 [[CONFLICT_RDX]], [[FOUND_CONFLICT9]]
326+
; CHECK-NEXT: [[BOUND011:%.*]] = icmp ult ptr [[DST_2]], [[SCEVGEP2]]
327+
; CHECK-NEXT: [[BOUND112:%.*]] = icmp ult ptr [[SRC_1]], [[SCEVGEP1]]
328+
; CHECK-NEXT: [[FOUND_CONFLICT13:%.*]] = and i1 [[BOUND011]], [[BOUND112]]
329+
; CHECK-NEXT: [[CONFLICT_RDX14:%.*]] = or i1 [[CONFLICT_RDX10]], [[FOUND_CONFLICT13]]
330+
; CHECK-NEXT: [[BOUND015:%.*]] = icmp ult ptr [[DST_2]], [[SCEVGEP3]]
331+
; CHECK-NEXT: [[BOUND116:%.*]] = icmp ult ptr [[SRC_2]], [[SCEVGEP1]]
332+
; CHECK-NEXT: [[FOUND_CONFLICT17:%.*]] = and i1 [[BOUND015]], [[BOUND116]]
333+
; CHECK-NEXT: [[CONFLICT_RDX18:%.*]] = or i1 [[CONFLICT_RDX14]], [[FOUND_CONFLICT17]]
334+
; CHECK-NEXT: br i1 [[CONFLICT_RDX18]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
335+
; CHECK: vector.ph:
336+
; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[UMAX19]], -4
337+
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
338+
; CHECK: vector.body:
339+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
340+
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[INDEX]]
341+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4, !alias.scope [[META22:![0-9]+]]
342+
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[INDEX]]
343+
; CHECK-NEXT: [[WIDE_LOAD20:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8, !alias.scope [[META25:![0-9]+]]
344+
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr nusw i32, ptr [[DST_1]], i64 [[INDEX]]
345+
; CHECK-NEXT: store <4 x i32> [[WIDE_LOAD]], ptr [[TMP4]], align 4, !alias.scope [[META27:![0-9]+]], !noalias [[META29:![0-9]+]]
346+
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[INDEX]]
347+
; CHECK-NEXT: store <4 x i64> [[WIDE_LOAD20]], ptr [[TMP5]], align 8, !alias.scope [[META31:![0-9]+]], !noalias [[META32:![0-9]+]]
348+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
349+
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
350+
; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP33:![0-9]+]]
351+
; CHECK: middle.block:
352+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX19]], [[N_VEC]]
353+
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
354+
; CHECK: scalar.ph:
355+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_MEMCHECK]] ]
356+
; CHECK-NEXT: br label [[LOOP:%.*]]
357+
; CHECK: loop:
358+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
359+
; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[IV]]
360+
; CHECK-NEXT: [[LD_SRC_1:%.*]] = load i32, ptr [[GEP_SRC_1]], align 4
361+
; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[IV]]
362+
; CHECK-NEXT: [[LD_SRC_2:%.*]] = load i64, ptr [[GEP_SRC_2]], align 8
363+
; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr nusw i32, ptr [[DST_1]], i64 [[IV]]
364+
; CHECK-NEXT: store i32 [[LD_SRC_1]], ptr [[GEP_DST_1]], align 4
365+
; CHECK-NEXT: [[GEP_DST_2:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[IV]]
366+
; CHECK-NEXT: store i64 [[LD_SRC_2]], ptr [[GEP_DST_2]], align 8
367+
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
368+
; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[IV_NEXT]], [[UMAX19]]
369+
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP34:![0-9]+]]
370+
; CHECK: exit:
371+
; CHECK-NEXT: ret void
372+
;
373+
; FORCED_OPTSIZE-LABEL: @different_load_store_pairs(
374+
; FORCED_OPTSIZE-NEXT: entry:
375+
; FORCED_OPTSIZE-NEXT: br label [[LOOP:%.*]]
376+
; FORCED_OPTSIZE: loop:
377+
; FORCED_OPTSIZE-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
378+
; FORCED_OPTSIZE-NEXT: [[GEP_SRC_1:%.*]] = getelementptr i32, ptr [[SRC_1:%.*]], i64 [[IV]]
379+
; FORCED_OPTSIZE-NEXT: [[LD_SRC_1:%.*]] = load i32, ptr [[GEP_SRC_1]], align 4
380+
; FORCED_OPTSIZE-NEXT: [[GEP_SRC_2:%.*]] = getelementptr i64, ptr [[SRC_2:%.*]], i64 [[IV]]
381+
; FORCED_OPTSIZE-NEXT: [[LD_SRC_2:%.*]] = load i64, ptr [[GEP_SRC_2]], align 8
382+
; FORCED_OPTSIZE-NEXT: [[GEP_DST_1:%.*]] = getelementptr nusw i32, ptr [[DST_1:%.*]], i64 [[IV]]
383+
; FORCED_OPTSIZE-NEXT: store i32 [[LD_SRC_1]], ptr [[GEP_DST_1]], align 4
384+
; FORCED_OPTSIZE-NEXT: [[GEP_DST_2:%.*]] = getelementptr nusw i64, ptr [[DST_2:%.*]], i64 [[IV]]
385+
; FORCED_OPTSIZE-NEXT: store i64 [[LD_SRC_2]], ptr [[GEP_DST_2]], align 8
386+
; FORCED_OPTSIZE-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
387+
; FORCED_OPTSIZE-NEXT: [[COND:%.*]] = icmp ult i64 [[IV_NEXT]], [[N:%.*]]
388+
; FORCED_OPTSIZE-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
389+
; FORCED_OPTSIZE: exit:
390+
; FORCED_OPTSIZE-NEXT: ret void
391+
;
392+
entry:
393+
br label %loop
394+
395+
loop:
396+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
397+
%gep.src.1 = getelementptr i32, ptr %src.1, i64 %iv
398+
%ld.src.1 = load i32, ptr %gep.src.1
399+
%gep.src.2 = getelementptr i64, ptr %src.2, i64 %iv
400+
%ld.src.2 = load i64, ptr %gep.src.2
401+
%gep.dst.1 = getelementptr nusw i32, ptr %dst.1, i64 %iv
402+
store i32 %ld.src.1, ptr %gep.dst.1
403+
%gep.dst.2 = getelementptr nusw i64, ptr %dst.2, i64 %iv
404+
store i64 %ld.src.2, ptr %gep.dst.2
405+
%iv.next = add nuw nsw i64 %iv, 1
406+
%cond = icmp ult i64 %iv.next, %n
407+
br i1 %cond, label %loop, label %exit
408+
409+
exit:
410+
ret void
411+
}
303412

304413
define dso_local void @forced_optsize(ptr noalias nocapture readonly %x_p, ptr noalias nocapture readonly %y_p, ptr noalias nocapture %z_p) minsize optsize {
305414
; CHECK-LABEL: @forced_optsize(
@@ -318,15 +427,15 @@ define dso_local void @forced_optsize(ptr noalias nocapture readonly %x_p, ptr n
318427
; CHECK-NEXT: store <2 x i64> [[TMP2]], ptr [[TMP3]], align 8
319428
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
320429
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
321-
; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
430+
; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP35:![0-9]+]]
322431
; CHECK: middle.block:
323432
; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]
324433
; CHECK: scalar.ph:
325434
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
326435
; CHECK: for.cond.cleanup:
327436
; CHECK-NEXT: ret void
328437
; CHECK: for.body:
329-
; CHECK-NEXT: br i1 poison, label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]
438+
; CHECK-NEXT: br i1 poison, label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP36:![0-9]+]]
330439
;
331440
; FORCED_OPTSIZE-LABEL: @forced_optsize(
332441
; FORCED_OPTSIZE-NEXT: entry:

‎llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,57 @@ exit:
177177
ret void
178178
}
179179

180+
define void @steps_match_two_loadstores_different_access_sizes(ptr %src.1, ptr %src.2, ptr %dst.1, ptr %dst.2, i64 %n) {
181+
; CHECK-LABEL: define void @steps_match_two_loadstores_different_access_sizes(
182+
; CHECK-SAME: ptr [[SRC_1:%.*]], ptr [[SRC_2:%.*]], ptr [[DST_1:%.*]], ptr [[DST_2:%.*]], i64 [[N:%.*]]) {
183+
; CHECK-NEXT: [[ENTRY:.*:]]
184+
; CHECK-NEXT: [[SRC_25:%.*]] = ptrtoint ptr [[SRC_2]] to i64
185+
; CHECK-NEXT: [[SRC_13:%.*]] = ptrtoint ptr [[SRC_1]] to i64
186+
; CHECK-NEXT: [[DST_12:%.*]] = ptrtoint ptr [[DST_1]] to i64
187+
; CHECK-NEXT: [[DST_21:%.*]] = ptrtoint ptr [[DST_2]] to i64
188+
; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
189+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4
190+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], [[SCALAR_PH:label %.*]], label %[[VECTOR_MEMCHECK:.*]]
191+
; CHECK: [[VECTOR_MEMCHECK]]:
192+
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[DST_21]], [[DST_12]]
193+
; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
194+
; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[DST_12]], [[SRC_13]]
195+
; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
196+
; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
197+
; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[DST_12]], [[SRC_25]]
198+
; CHECK-NEXT: [[DIFF_CHECK6:%.*]] = icmp ult i64 [[TMP2]], 32
199+
; CHECK-NEXT: [[CONFLICT_RDX7:%.*]] = or i1 [[CONFLICT_RDX]], [[DIFF_CHECK6]]
200+
; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[DST_21]], [[SRC_13]]
201+
; CHECK-NEXT: [[DIFF_CHECK8:%.*]] = icmp ult i64 [[TMP3]], 32
202+
; CHECK-NEXT: [[CONFLICT_RDX9:%.*]] = or i1 [[CONFLICT_RDX7]], [[DIFF_CHECK8]]
203+
; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[DST_21]], [[SRC_25]]
204+
; CHECK-NEXT: [[DIFF_CHECK10:%.*]] = icmp ult i64 [[TMP4]], 32
205+
; CHECK-NEXT: [[CONFLICT_RDX11:%.*]] = or i1 [[CONFLICT_RDX9]], [[DIFF_CHECK10]]
206+
; CHECK-NEXT: br i1 [[CONFLICT_RDX11]], [[SCALAR_PH]], [[VECTOR_PH:label %.*]]
207+
;
208+
entry:
209+
br label %loop
210+
211+
loop:
212+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
213+
%gep.src.1 = getelementptr i64, ptr %src.1, i64 %iv
214+
%ld.src.1 = load i64, ptr %gep.src.1
215+
%ld.src.1.i32 = trunc i64 %ld.src.1 to i32
216+
%gep.src.2 = getelementptr i64, ptr %src.2, i64 %iv
217+
%ld.src.2 = load i64, ptr %gep.src.2
218+
%add = add i64 %ld.src.1, %ld.src.2
219+
%gep.dst.1 = getelementptr nusw i64, ptr %dst.1, i64 %iv
220+
store i32 %ld.src.1.i32, ptr %gep.dst.1
221+
%gep.dst.2 = getelementptr nusw i64, ptr %dst.2, i64 %iv
222+
store i64 %add, ptr %gep.dst.2
223+
%iv.next = add nuw nsw i64 %iv, 1
224+
%cond = icmp ult i64 %iv.next, %n
225+
br i1 %cond, label %loop, label %exit
226+
227+
exit:
228+
ret void
229+
}
230+
180231
; Full no-overlap checks are required instead of difference checks, as
181232
; one of the add-recs used is invariant in the inner loop.
182233
; Test case for PR57315.

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