Added observations for tests.

Author: Pravin Jagtap

llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir

@@ -1,6 +1,9 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn -mcpu=gfx908 %s -o - -run-pass prologepilog,machine-cp -verify-machineinstrs | FileCheck -check-prefix=GFX908 %s
 
+# When VGPRs are available for spilling, prologepilog marks the tuple implicit-def as well as implicit in the first spill instruction.
+# As a consequence, machine-cp would NOT delete agpr2 copy here.
+
 ---
 name:  agpr-spill-to-vgpr-machine-cp
 tracksRegLiveness: true
@@ -30,6 +33,9 @@ body: |
     S_ENDPGM 0
 ...
 
+# When VGPRs are NOT available for spilling (stack is used), prologepilog marks the tuple implicit-def only and NOT implicit.
+# As a consequence, machine-cp would delete agpr2 copy here.
+
 ---
 name:  agpr-spill-to-vgpr-to-stack-machine-cp
 tracksRegLiveness: true

llvm/test/CodeGen/AMDGPU/av-spill-to-vgpr-and-stack.mir

@@ -1,6 +1,9 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn -mcpu=gfx908 %s -o - -run-pass prologepilog -verify-machineinstrs | FileCheck -check-prefix=GFX908 %s
 
+# During spill expansion, when VGPRs are available for spilling (stack is unused), tuple is being marked as
+# implicit-def as well as implicit in the first spill instrunction.
+
 ---
 name:  agpr-spill-to-vgpr
 tracksRegLiveness: true
@@ -30,6 +33,9 @@ body: |
     S_ENDPGM 0
 ...
 
+# During spill expansion, when VGPRs are NOT available for spilling (stack is used), tuple is being marked as
+# implicit-def ONLY and NOT implicit in the first spill instrunction.
+
 ---
 name:  agpr-spill-to-vgpr-to-stack
 tracksRegLiveness: true