fixup! resolve comments

Author: 4vtomat

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -1046,8 +1046,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     if (!isInt<32>(Imm) && isUInt<32>(Imm) && hasAllWUsers(Node))
       Imm = SignExtend64<32>(Imm);
 
-    if (hasAllWUsers(Node) && isApplicableToPLI(Imm) &&
-        Subtarget->enablePExtCodeGen()) {
+    if (Subtarget->enablePExtCodeGen() && isApplicableToPLI(Imm) &&
+        hasAllWUsers(Node)) {
       // If its 4 packed 8-bit integers or 2 packed signed 16-bit integers, we
       // can simply copy lower 32 bits to higher 32 bits to make it able to
       // rematerialize to PLI_B or PLI_H
@@ -2675,12 +2675,19 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       return;
     }
     if (Subtarget->enablePExtCodeGen()) {
-      if (((VT == MVT::v4i16 || VT == MVT::v8i8) && SrcVT == MVT::i64) ||
-          ((SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) && VT == MVT::i64)) {
+      bool Is32BitCast =
+          (VT == MVT::i32 && (SrcVT == MVT::v4i8 || SrcVT == MVT::v2i16)) ||
+          (SrcVT == MVT::i32 && (VT == MVT::v4i8 || VT == MVT::v2i16));
+      bool Is64BitCast =
+          (VT == MVT::i64 && (SrcVT == MVT::v8i8 || SrcVT == MVT::v4i16 ||
+                              SrcVT == MVT::v2i32)) ||
+          (SrcVT == MVT::i64 &&
+           (VT == MVT::v8i8 || VT == MVT::v4i16 || VT == MVT::v2i32));
+      if (Is32BitCast || Is64BitCast) {
         ReplaceUses(SDValue(Node, 0), Node->getOperand(0));
         CurDAG->RemoveDeadNode(Node);
+        return;
       }
-      return;
     }
     break;
   }

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -10536,18 +10536,9 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
       return SDValue();
     SDValue Extracted = DAG.getBitcast(XLenVT, Vec);
     unsigned ElemWidth = EltVT.getSizeInBits();
-    if (auto *IdxC = dyn_cast<ConstantSDNode>(Idx)) {
-      unsigned Idx = IdxC->getZExtValue();
-      unsigned Shamt = Idx * ElemWidth;
-      if (Shamt > 0)
-        Extracted = DAG.getNode(ISD::SRL, DL, XLenVT,
-                                DAG.getConstant(Shamt, DL, XLenVT));
-    } else {
-      SDValue Shamt = DAG.getNode(ISD::MUL, DL, XLenVT, Idx,
-                                  DAG.getConstant(ElemWidth, DL, XLenVT));
-      Extracted = DAG.getNode(ISD::SRL, DL, XLenVT, Shamt);
-    }
-    return DAG.getNode(ISD::TRUNCATE, DL, EltVT, Extracted);
+    SDValue Shamt = DAG.getNode(ISD::MUL, DL, XLenVT, Idx,
+                                DAG.getConstant(ElemWidth, DL, XLenVT));
+    return DAG.getNode(ISD::SRL, DL, XLenVT, Extracted, Shamt);
   }
 
   // If this is a fixed vector, we need to convert it to a scalable vector.

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

@@ -1472,11 +1472,7 @@ def SDT_RISCVPASUB : SDTypeProfile<1, 2, [SDTCisVec<0>,
                                           SDTCisSameAs<0, 1>,
                                           SDTCisSameAs<0, 2>]>;
 def riscv_pasub : RVSDNode<"PASUB", SDT_RISCVPASUB>;
-def SDT_RISCVPASUBU : SDTypeProfile<1, 2, [SDTCisVec<0>,
-                                           SDTCisInt<0>,
-                                           SDTCisSameAs<0, 1>,
-                                           SDTCisSameAs<0, 2>]>;
-def riscv_pasubu : RVSDNode<"PASUBU", SDT_RISCVPASUBU>;
+def riscv_pasubu : RVSDNode<"PASUBU", SDT_RISCVPASUB>;
 
 let Predicates = [HasStdExtP] in {
   def : PatGpr<abs, ABS>;

llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll

@@ -472,6 +472,30 @@ define void @test_pli_b_negative(ptr %ret_ptr) {
   ret void
 }
 
+define void @test_extract_vector_16(ptr %ret_ptr, ptr %a_ptr) {
+; CHECK-LABEL: test_extract_vector_16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a1, 0(a1)
+; CHECK-NEXT:    sh a1, 0(a0)
+; CHECK-NEXT:    ret
+  %a = load <2 x i16>, ptr %a_ptr
+  %extracted = extractelement <2 x i16> %a, i32 0
+  store i16 %extracted, ptr %ret_ptr
+  ret void
+}
+
+define void @test_extract_vector_8(ptr %ret_ptr, ptr %a_ptr) {
+; CHECK-LABEL: test_extract_vector_8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a1, 0(a1)
+; CHECK-NEXT:    sb a1, 0(a0)
+; CHECK-NEXT:    ret
+  %a = load <4 x i8>, ptr %a_ptr
+  %extracted = extractelement <4 x i8> %a, i32 0
+  store i8 %extracted, ptr %ret_ptr
+  ret void
+}
+
 ; Intrinsic declarations
 declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>)
 declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>)

llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll

@@ -459,6 +459,42 @@ define void @test_pli_w(ptr %ret_ptr) {
   ret void
 }
 
+define void @test_extract_vector_16(ptr %ret_ptr, ptr %a_ptr) {
+; CHECK-LABEL: test_extract_vector_16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ld a1, 0(a1)
+; CHECK-NEXT:    sh a1, 0(a0)
+; CHECK-NEXT:    ret
+  %a = load <4 x i16>, ptr %a_ptr
+  %extracted = extractelement <4 x i16> %a, i32 0
+  store i16 %extracted, ptr %ret_ptr
+  ret void
+}
+
+define void @test_extract_vector_8(ptr %ret_ptr, ptr %a_ptr) {
+; CHECK-LABEL: test_extract_vector_8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ld a1, 0(a1)
+; CHECK-NEXT:    sb a1, 0(a0)
+; CHECK-NEXT:    ret
+  %a = load <8 x i8>, ptr %a_ptr
+  %extracted = extractelement <8 x i8> %a, i32 0
+  store i8 %extracted, ptr %ret_ptr
+  ret void
+}
+
+define void @test_extract_vector_32(ptr %ret_ptr, ptr %a_ptr) {
+; CHECK-LABEL: test_extract_vector_32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ld a1, 0(a1)
+; CHECK-NEXT:    sw a1, 0(a0)
+; CHECK-NEXT:    ret
+  %a = load <2 x i32>, ptr %a_ptr
+  %extracted = extractelement <2 x i32> %a, i32 0
+  store i32 %extracted, ptr %ret_ptr
+  ret void
+}
+
 ; Intrinsic declarations
 declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>)
 declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>)