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[AMDGPU][True16][MC] test update for v_mul_f16 in true16 (#119314)
This is a NFC change. Update mc test for v_mul_f16 in true16 format. MC source change was done by previous patch and automatically enabled by t16 pesudo
1 parent 2a92290 commit f9a9173

17 files changed

+572
-342
lines changed

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1822,8 +1822,7 @@ defm V_ADD_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x032, "v
18221822
defm V_SUB_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x033, "v_sub_f16">;
18231823
defm V_SUBREV_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
18241824
defm V_SUBREV_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
1825-
defm V_MUL_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
1826-
defm V_MUL_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x035, "v_mul_f16">;
1825+
defm V_MUL_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x035, "v_mul_f16">;
18271826
defm V_FMAC_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x036, "v_fmac_f16">;
18281827
defm V_LDEXP_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x03b, "v_ldexp_f16">;
18291828
defm V_LDEXP_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x03b, "v_ldexp_f16">;

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2.s‎

Lines changed: 45 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1612,50 +1612,65 @@ v_mul_dx9_zero_f32 v5, src_scc, v2
16121612
v_mul_dx9_zero_f32 v255, 0xaf123456, v255
16131613
// GFX11: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf]
16141614

1615-
v_mul_f16 v5, v1, v2
1616-
// GFX11: v_mul_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6a]
1615+
v_mul_f16 v5.l, v1.l, v2.l
1616+
// GFX11: v_mul_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x6a]
16171617

1618-
v_mul_f16 v5, v127, v2
1619-
// GFX11: v_mul_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6a]
1618+
v_mul_f16 v5.l, v127.l, v2.l
1619+
// GFX11: v_mul_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x6a]
16201620

1621-
v_mul_f16 v5, s1, v2
1622-
// GFX11: v_mul_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6a]
1621+
v_mul_f16 v5.l, s1, v2.l
1622+
// GFX11: v_mul_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x6a]
16231623

1624-
v_mul_f16 v5, s105, v2
1625-
// GFX11: v_mul_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6a]
1624+
v_mul_f16 v5.l, s105, v2.l
1625+
// GFX11: v_mul_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x6a]
16261626

1627-
v_mul_f16 v5, vcc_lo, v2
1628-
// GFX11: v_mul_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6a]
1627+
v_mul_f16 v5.l, vcc_lo, v2.l
1628+
// GFX11: v_mul_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x6a]
16291629

1630-
v_mul_f16 v5, vcc_hi, v2
1631-
// GFX11: v_mul_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6a]
1630+
v_mul_f16 v5.l, vcc_hi, v2.l
1631+
// GFX11: v_mul_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x6a]
16321632

1633-
v_mul_f16 v5, ttmp15, v2
1634-
// GFX11: v_mul_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6a]
1633+
v_mul_f16 v5.l, ttmp15, v2.l
1634+
// GFX11: v_mul_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x6a]
16351635

1636-
v_mul_f16 v5, m0, v2
1637-
// GFX11: v_mul_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6a]
1636+
v_mul_f16 v5.l, m0, v2.l
1637+
// GFX11: v_mul_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x6a]
16381638

1639-
v_mul_f16 v5, exec_lo, v2
1640-
// GFX11: v_mul_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6a]
1639+
v_mul_f16 v5.l, exec_lo, v2.l
1640+
// GFX11: v_mul_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x6a]
16411641

1642-
v_mul_f16 v5, exec_hi, v2
1643-
// GFX11: v_mul_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6a]
1642+
v_mul_f16 v5.l, exec_hi, v2.l
1643+
// GFX11: v_mul_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x6a]
16441644

1645-
v_mul_f16 v5, null, v2
1646-
// GFX11: v_mul_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6a]
1645+
v_mul_f16 v5.l, null, v2.l
1646+
// GFX11: v_mul_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x6a]
16471647

1648-
v_mul_f16 v5, -1, v2
1649-
// GFX11: v_mul_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6a]
1648+
v_mul_f16 v5.l, -1, v2.l
1649+
// GFX11: v_mul_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x6a]
16501650

1651-
v_mul_f16 v5, 0.5, v2
1652-
// GFX11: v_mul_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6a]
1651+
v_mul_f16 v5.l, 0.5, v2.l
1652+
// GFX11: v_mul_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x6a]
16531653

1654-
v_mul_f16 v5, src_scc, v2
1655-
// GFX11: v_mul_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6a]
1654+
v_mul_f16 v5.l, src_scc, v2.l
1655+
// GFX11: v_mul_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x6a]
16561656

1657-
v_mul_f16 v127, 0xfe0b, v127
1658-
// GFX11: v_mul_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
1657+
v_mul_f16 v127.l, 0xfe0b, v127.l
1658+
// GFX11: v_mul_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00]
1659+
1660+
v_mul_f16 v5.l, v1.h, v2.l
1661+
// GFX11: v_mul_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x6a]
1662+
1663+
v_mul_f16 v5.l, v127.h, v2.l
1664+
// GFX11: v_mul_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x6a]
1665+
1666+
v_mul_f16 v127.l, 0.5, v127.l
1667+
// GFX11: v_mul_f16_e32 v127.l, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfe,0x6a]
1668+
1669+
v_mul_f16 v5.h, src_scc, v2.h
1670+
// GFX11: v_mul_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x6b]
1671+
1672+
v_mul_f16 v127.h, 0xfe0b, v127.h
1673+
// GFX11: v_mul_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00]
16591674

16601675
v_mul_f32 v5, v1, v2
16611676
// GFX11: v_mul_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s‎

Lines changed: 37 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1245,47 +1245,56 @@ v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:
12451245
v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
12461246
// GFX11: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30]
12471247

1248-
v_mul_f16 v5, v1, v2 quad_perm:[3,2,1,0]
1249-
// GFX11: v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff]
1248+
v_mul_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
1249+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff]
12501250

1251-
v_mul_f16 v5, v1, v2 quad_perm:[0,1,2,3]
1252-
// GFX11: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff]
1251+
v_mul_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
1252+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff]
12531253

1254-
v_mul_f16 v5, v1, v2 row_mirror
1255-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff]
1254+
v_mul_f16 v5.l, v1.l, v2.l row_mirror
1255+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff]
12561256

1257-
v_mul_f16 v5, v1, v2 row_half_mirror
1258-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff]
1257+
v_mul_f16 v5.l, v1.l, v2.l row_half_mirror
1258+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff]
12591259

1260-
v_mul_f16 v5, v1, v2 row_shl:1
1261-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff]
1260+
v_mul_f16 v5.l, v1.l, v2.l row_shl:1
1261+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff]
12621262

1263-
v_mul_f16 v5, v1, v2 row_shl:15
1264-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff]
1263+
v_mul_f16 v5.l, v1.l, v2.l row_shl:15
1264+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff]
12651265

1266-
v_mul_f16 v5, v1, v2 row_shr:1
1267-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff]
1266+
v_mul_f16 v5.l, v1.l, v2.l row_shr:1
1267+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff]
12681268

1269-
v_mul_f16 v5, v1, v2 row_shr:15
1270-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff]
1269+
v_mul_f16 v5.l, v1.l, v2.l row_shr:15
1270+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff]
12711271

1272-
v_mul_f16 v5, v1, v2 row_ror:1
1273-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff]
1272+
v_mul_f16 v5.l, v1.l, v2.l row_ror:1
1273+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff]
12741274

1275-
v_mul_f16 v5, v1, v2 row_ror:15
1276-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff]
1275+
v_mul_f16 v5.l, v1.l, v2.l row_ror:15
1276+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff]
12771277

1278-
v_mul_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1279-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff]
1278+
v_mul_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
1279+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff]
12801280

1281-
v_mul_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1282-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01]
1281+
v_mul_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
1282+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01]
12831283

1284-
v_mul_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1285-
// GFX11: v_mul_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13]
1284+
v_mul_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
1285+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13]
12861286

1287-
v_mul_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1288-
// GFX11: v_mul_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30]
1287+
v_mul_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
1288+
// GFX11: v_mul_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30]
1289+
1290+
v_mul_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
1291+
// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x5f,0x01,0x01]
1292+
1293+
v_mul_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1294+
// GFX11: v_mul_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x6b,0x81,0x60,0x09,0x13]
1295+
1296+
v_mul_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1297+
// GFX11: v_mul_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6b,0xff,0x6f,0xf5,0x30]
12891298

12901299
v_mul_f32 v5, v1, v2 quad_perm:[3,2,1,0]
12911300
// GFX11: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s‎

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -289,14 +289,23 @@ v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
289289
v_mul_dx9_zero_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
290290
// GFX11: v_mul_dx9_zero_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00]
291291

292-
v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
293-
// GFX11: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
292+
v_mul_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
293+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
294294

295-
v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
296-
// GFX11: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
295+
v_mul_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
296+
// GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05]
297297

298-
v_mul_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
299-
// GFX11: v_mul_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00]
298+
v_mul_f16 v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
299+
// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00]
300+
301+
v_mul_f16 v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
302+
// GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x77,0x39,0x05]
303+
304+
v_mul_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
305+
// GFX11: v_mul_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0b,0x6b,0x81,0x77,0x39,0x05]
306+
307+
v_mul_f16 v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
308+
// GFX11: v_mul_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x6b,0xff,0x00,0x00,0x00]
300309

301310
v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
302311
// GFX11: v_mul_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s‎

Lines changed: 45 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -281,32 +281,59 @@ v_min_f16_e32 v5.l, v1.l, v255.l
281281
v_min_f16_e32 v5.l, v255.l, v2.l
282282
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
283283

284-
v_mul_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
285-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
284+
v_mul_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
285+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
286286

287-
v_mul_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
288-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
287+
v_mul_f16_dpp v255.h, v1.h, v2.h quad_perm:[3,2,1,0]
288+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
289289

290-
v_mul_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
291-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
290+
v_mul_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
291+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
292292

293-
v_mul_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
294-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
293+
v_mul_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0]
294+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
295295

296-
v_mul_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
297-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
296+
v_mul_f16_dpp v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
297+
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
298298

299-
v_mul_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
300-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
299+
v_mul_f16_dpp v5.h, v1.h, v255.h quad_perm:[3,2,1,0]
300+
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
301301

302-
v_mul_f16_e32 v255, v1, v2
303-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
302+
v_mul_f16_dpp v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
303+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
304304

305-
v_mul_f16_e32 v5, v1, v255
306-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
305+
v_mul_f16_dpp v5.h, v255.h, v2.h quad_perm:[3,2,1,0]
306+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
307307

308-
v_mul_f16_e32 v5, v255, v2
309-
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
308+
v_mul_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
309+
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
310+
311+
v_mul_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0]
312+
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
313+
314+
v_mul_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
315+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
316+
317+
v_mul_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
318+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
319+
320+
v_mul_f16_e32 v255.h, v1.h, v2.h
321+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
322+
323+
v_mul_f16_e32 v255.l, v1.l, v2.l
324+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
325+
326+
v_mul_f16_e32 v5.h, v1.h, v255.h
327+
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
328+
329+
v_mul_f16_e32 v5.h, v255.h, v2.h
330+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
331+
332+
v_mul_f16_e32 v5.l, v1.l, v255.l
333+
// GFX11: :[[@LINE-1]]:27: error: invalid operand for instruction
334+
335+
v_mul_f16_e32 v5.l, v255.l, v2.l
336+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
310337

311338
v_sub_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
312339
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction

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