Skip to content

Commit fa5dd24

Browse files
committed
simplify RVPUnary#
1 parent 0d5b680 commit fa5dd24

File tree

1 file changed

+18
-16
lines changed

1 file changed

+18
-16
lines changed

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

Lines changed: 18 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -60,37 +60,38 @@ class RVPUnaryImm8<bits<8> funct8, string opcodestr>
6060
}
6161

6262
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
63-
class RVPUnaryImm5<bits<3> f, string opcodestr>
64-
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd),
65-
(ins GPR:$rs1, uimm5:$uimm5), opcodestr, "$rd, $rs1, $uimm5"> {
66-
bits<5> uimm5;
63+
class RVPUnary<bits<3> f, string opcodestr, dag operands, string argstr>
64+
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), operands, opcodestr, argstr> {
65+
bits<5> imm;
66+
bits<5> rs1;
67+
6768
let Inst{31} = 0b1;
6869
let Inst{30-28} = f;
6970
let Inst{27} = 0b0;
71+
let Inst{19-15} = rs1;
72+
}
73+
74+
class RVPUnaryImm5<bits<3> f, string opcodestr>
75+
: RVPUnary<f, opcodestr, (ins GPR:$rs1, uimm5:$uimm5), "$rd, $rs1, $uimm5"> {
76+
bits<5> uimm5;
77+
78+
let imm = uimm5;
7079
let Inst{26-25} = 0b01;
7180
let Inst{24-20} = uimm5;
7281
}
7382

74-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
7583
class RVPUnaryImm4<bits<3> f, string opcodestr>
76-
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd),
77-
(ins GPR:$rs1, uimm4:$uimm4), opcodestr, "$rd, $rs1, $uimm4"> {
84+
: RVPUnary<f, opcodestr, (ins GPR:$rs1, uimm4:$uimm4), "$rd, $rs1, $uimm4"> {
7885
bits<4> uimm4;
79-
let Inst{31} = 0b1;
80-
let Inst{30-28} = f;
81-
let Inst{27} = 0b0;
86+
8287
let Inst{26-24} = 0b001;
8388
let Inst{23-20} = uimm4;
8489
}
8590

86-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
8791
class RVPUnaryImm3<bits<3> f, string opcodestr>
88-
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd),
89-
(ins GPR:$rs1, uimm3:$uimm3), opcodestr, "$rd, $rs1, $uimm3"> {
92+
: RVPUnary<f, opcodestr, (ins GPR:$rs1, uimm3:$uimm3), "$rd, $rs1, $uimm3"> {
9093
bits<3> uimm3;
91-
let Inst{31} = 0b1;
92-
let Inst{30-28} = f;
93-
let Inst{27} = 0b0;
94+
9495
let Inst{26-23} = 0b0001;
9596
let Inst{22-20} = uimm3;
9697
}
@@ -157,3 +158,4 @@ let Predicates = [HasStdExtP] in
157158
def PLUI_H : RVPUnaryImm10<0b1111000, "plui.h">;
158159
let Predicates = [HasStdExtP, IsRV64] in
159160
def PLUI_W : RVPUnaryImm10<0b1111001, "plui.w">;
161+

0 commit comments

Comments
 (0)