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[InstCombine] Use m_Specific rather than m_Value (#157524)
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2 files changed

+52
-47
lines changed

2 files changed

+52
-47
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2723,14 +2723,14 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
27232723
// Replacing a sub and at least one min with an icmp
27242724
// and a zext is a potential improvement.
27252725
if (match(Op0, m_c_SMin(m_c_NSWAdd(m_Value(X), m_One()), m_Value(Y))) &&
2726-
match(Op1, m_c_SMin(m_Value(X), m_Value(Y))) &&
2726+
match(Op1, m_c_SMin(m_Specific(X), m_Specific(Y))) &&
27272727
I.getType()->getScalarSizeInBits() != 1 &&
27282728
(Op0->hasOneUse() || Op1->hasOneUse())) {
27292729
Value *Cond = Builder.CreateICmpSLT(X, Y);
27302730
return new ZExtInst(Cond, I.getType());
27312731
}
27322732
if (match(Op0, m_c_UMin(m_c_NUWAdd(m_Value(X), m_One()), m_Value(Y))) &&
2733-
match(Op1, m_c_UMin(m_Value(X), m_Value(Y))) &&
2733+
match(Op1, m_c_UMin(m_Specific(X), m_Specific(Y))) &&
27342734
I.getType()->getScalarSizeInBits() != 1 &&
27352735
(Op0->hasOneUse() || Op1->hasOneUse())) {
27362736
Value *Cond = Builder.CreateICmpULT(X, Y);

‎llvm/test/Transforms/InstCombine/min-zext.ll‎

Lines changed: 50 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
12
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
23

34
define i32 @test_smin(i32 %arg0, i32 %arg1) {
45
; CHECK-LABEL: define i32 @test_smin(
5-
; CHECK-NEXT: %v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
6-
; CHECK-NEXT: %v1 = add nsw i32 %arg0, 1
7-
; CHECK-NEXT: %v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
8-
; CHECK-NEXT: %v3 = sub i32 %v2, %v0
9-
; CHECK-NEXT: ret i32 %v3
6+
; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
7+
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[ARG0]], [[ARG1]]
8+
; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i32
9+
; CHECK-NEXT: ret i32 [[V3]]
1010
;
1111
%v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
1212
%v1 = add nsw i32 %arg0, 1
@@ -17,11 +17,10 @@ define i32 @test_smin(i32 %arg0, i32 %arg1) {
1717

1818
define i32 @test_umin(i32 %arg0, i32 %arg1) {
1919
; CHECK-LABEL: define i32 @test_umin(
20-
; CHECK-NEXT: %v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)
21-
; CHECK-NEXT: %v1 = add nuw i32 %arg0, 1
22-
; CHECK-NEXT: %v2 = tail call i32 @llvm.umin.i32(i32 %v1, i32 %arg1)
23-
; CHECK-NEXT: %v3 = sub i32 %v2, %v0
24-
; CHECK-NEXT: ret i32 %v3
20+
; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
21+
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[ARG0]], [[ARG1]]
22+
; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i32
23+
; CHECK-NEXT: ret i32 [[V3]]
2524
;
2625
%v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)
2726
%v1 = add nuw i32 %arg0, 1
@@ -32,9 +31,10 @@ define i32 @test_umin(i32 %arg0, i32 %arg1) {
3231

3332
define i1 @test_smin_i1(i1 %arg0, i1 %arg1) {
3433
; CHECK-LABEL: define i1 @test_smin_i1(
35-
; CHECK-NEXT: %v0 = or i1 %arg0, %arg1
36-
; CHECK-NEXT: %v3 = xor i1 %v0, true
37-
; CHECK-NEXT: ret i1 %v3
34+
; CHECK-SAME: i1 [[ARG0:%.*]], i1 [[ARG1:%.*]]) {
35+
; CHECK-NEXT: [[V0:%.*]] = or i1 [[ARG0]], [[ARG1]]
36+
; CHECK-NEXT: [[V3:%.*]] = xor i1 [[V0]], true
37+
; CHECK-NEXT: ret i1 [[V3]]
3838
;
3939
%v0 = tail call i1 @llvm.smin.i1(i1 %arg0, i1 %arg1)
4040
%v1 = add nsw i1 %arg0, 1
@@ -47,47 +47,50 @@ declare void @use(i2)
4747

4848
define i2 @test_smin_use_operands(i2 %arg0, i2 %arg1) {
4949
; CHECK-LABEL: define i2 @test_smin_use_operands(
50-
; CHECK-NEXT: %v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)
51-
; CHECK-NEXT: %v1 = add nsw i2 %arg0, 1
52-
; CHECK-NEXT: %v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)
53-
; CHECK-NEXT: %v3 = sub i2 %v2, %v0
54-
; CHECK-NEXT: call void @use(i2 %v2)
55-
; CHECK-NEXT: call void @use(i2 %v0)
56-
; CHECK-NEXT: ret i2 %v3
50+
; CHECK-SAME: i2 [[ARG0:%.*]], i2 [[ARG1:%.*]]) {
51+
; CHECK-NEXT: [[V0:%.*]] = tail call i2 @llvm.smin.i2(i2 [[ARG0]], i2 [[ARG1]])
52+
; CHECK-NEXT: [[V1:%.*]] = add nsw i2 [[ARG0]], 1
53+
; CHECK-NEXT: [[V2:%.*]] = tail call i2 @llvm.smin.i2(i2 [[V1]], i2 [[ARG1]])
54+
; CHECK-NEXT: [[V3:%.*]] = sub i2 [[V2]], [[V0]]
55+
; CHECK-NEXT: call void @use(i2 [[V2]])
56+
; CHECK-NEXT: call void @use(i2 [[V0]])
57+
; CHECK-NEXT: ret i2 [[V3]]
5758
;
5859
%v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)
5960
%v1 = add nsw i2 %arg0, 1
6061
%v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)
61-
%v3 = sub i2 %v2, %v0
62+
%v3 = sub i2 %v2, %v0
6263
call void @use(i2 %v2)
6364
call void @use(i2 %v0)
64-
ret i2 %v3
65+
ret i2 %v3
6566
}
6667

6768
define i2 @test_smin_use_operand(i2 %arg0, i2 %arg1) {
6869
; CHECK-LABEL: define i2 @test_smin_use_operand(
69-
; CHECK-NEXT: %v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)
70-
; CHECK-NEXT: %v1 = add nsw i2 %arg0, 1
71-
; CHECK-NEXT: %v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)
72-
; CHECK-NEXT: %v3 = sub i2 %v2, %v0
73-
; CHECK-NEXT: call void @use(i2 %v2)
74-
; CHECK-NEXT: ret i2 %v3
70+
; CHECK-SAME: i2 [[ARG0:%.*]], i2 [[ARG1:%.*]]) {
71+
; CHECK-NEXT: [[V1:%.*]] = add nsw i2 [[ARG0]], 1
72+
; CHECK-NEXT: [[V2:%.*]] = tail call i2 @llvm.smin.i2(i2 [[V1]], i2 [[ARG1]])
73+
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i2 [[ARG0]], [[ARG1]]
74+
; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i2
75+
; CHECK-NEXT: call void @use(i2 [[V2]])
76+
; CHECK-NEXT: ret i2 [[V3]]
7577
;
7678
%v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)
7779
%v1 = add nsw i2 %arg0, 1
7880
%v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)
79-
%v3 = sub i2 %v2, %v0
81+
%v3 = sub i2 %v2, %v0
8082
call void @use(i2 %v2)
81-
ret i2 %v3
83+
ret i2 %v3
8284
}
8385

8486
define i32 @test_smin_missing_nsw(i32 %arg0, i32 %arg1) {
8587
; CHECK-LABEL: define i32 @test_smin_missing_nsw(
86-
; CHECK-NEXT: %v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
87-
; CHECK-NEXT: %v1 = add i32 %arg0, 1
88-
; CHECK-NEXT: %v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
89-
; CHECK-NEXT: %v3 = sub i32 %v2, %v0
90-
; CHECK-NEXT: ret i32 %v3
88+
; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
89+
; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.smin.i32(i32 [[ARG0]], i32 [[ARG1]])
90+
; CHECK-NEXT: [[V1:%.*]] = add i32 [[ARG0]], 1
91+
; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.smin.i32(i32 [[V1]], i32 [[ARG1]])
92+
; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V2]], [[V0]]
93+
; CHECK-NEXT: ret i32 [[V3]]
9194
;
9295
%v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
9396
%v1 = add i32 %arg0, 1
@@ -98,11 +101,12 @@ define i32 @test_smin_missing_nsw(i32 %arg0, i32 %arg1) {
98101

99102
define i32 @test_umin_missing_nuw(i32 %arg0, i32 %arg1) {
100103
; CHECK-LABEL: define i32 @test_umin_missing_nuw(
101-
; CHECK-NEXT: %v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)
102-
; CHECK-NEXT: %v1 = add i32 %arg0, 1
103-
; CHECK-NEXT: %v2 = tail call i32 @llvm.umin.i32(i32 %v1, i32 %arg1)
104-
; CHECK-NEXT: %v3 = sub i32 %v2, %v0
105-
; CHECK-NEXT: ret i32 %v3
104+
; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
105+
; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.umin.i32(i32 [[ARG0]], i32 [[ARG1]])
106+
; CHECK-NEXT: [[V1:%.*]] = add i32 [[ARG0]], 1
107+
; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.umin.i32(i32 [[V1]], i32 [[ARG1]])
108+
; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V2]], [[V0]]
109+
; CHECK-NEXT: ret i32 [[V3]]
106110
;
107111
%v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)
108112
%v1 = add i32 %arg0, 1
@@ -113,11 +117,12 @@ define i32 @test_umin_missing_nuw(i32 %arg0, i32 %arg1) {
113117

114118
define i32 @test_mismatched_operands(i32 %arg0, i32 %arg1) {
115119
; CHECK-LABEL: define i32 @test_mismatched_operands(
116-
; CHECK-NEXT: %v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
117-
; CHECK-NEXT: %v1 = add nsw i32 %arg0, 1
118-
; CHECK-NEXT: %v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
119-
; CHECK-NEXT: %v3 = sub i32 %v0, %v2
120-
; CHECK-NEXT: ret i32 %v3
120+
; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
121+
; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.smin.i32(i32 [[ARG0]], i32 [[ARG1]])
122+
; CHECK-NEXT: [[V1:%.*]] = add nsw i32 [[ARG0]], 1
123+
; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.smin.i32(i32 [[V1]], i32 [[ARG1]])
124+
; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V0]], [[V2]]
125+
; CHECK-NEXT: ret i32 [[V3]]
121126
;
122127
%v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
123128
%v1 = add nsw i32 %arg0, 1

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