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mgoudarmgoudar
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Set MicroOpBufferSize and BufferSize to 0
i6400 and i6500 are in-order cores. hence set BufferSize and MicroBufferSize to 0
1 parent c5195f7 commit fc23bdf

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3 files changed

+32
-38
lines changed

3 files changed

+32
-38
lines changed

‎llvm/lib/Target/Mips/Mips32r6InstrInfo.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -984,7 +984,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
984984
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
985985
def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
986986

987-
let hasNoSchedulingInfo = 1 in {
987+
let hasNoSchedulingInfo = true in {
988988
def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
989989
}
990990
}
@@ -999,7 +999,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
999999
}
10001000

10011001
let AdditionalPredicates = [NotInMicroMips] in {
1002-
let hasNoSchedulingInfo = 1 in {
1002+
let hasNoSchedulingInfo = true in {
10031003
def GINVI : R6MMR6Rel, GINVI_ENC, GINVI_DESC, ISA_MIPS32R6, ASE_GINV;
10041004
def GINVT : R6MMR6Rel, GINVT_ENC, GINVT_DESC, ISA_MIPS32R6, ASE_GINV;
10051005
}

‎llvm/lib/Target/Mips/MipsScheduleI6400.td‎

Lines changed: 13 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88

99
def MipsI6400Model : SchedMachineModel {
1010
int IssueWidth = 2; // 2x dispatched per cycle
11-
int MicroOpBufferSize = 48; // min(48, 48, 64)
11+
int MicroOpBufferSize = 0;
1212
int LoadLatency = 3;
1313
int MispredictPenalty = 8;
1414

@@ -26,17 +26,17 @@ let SchedModel = MipsI6400Model in {
2626

2727
// AGEN Pipelines
2828
// ==============
29-
def I6400AGEN : ProcResource<1> { let BufferSize = 16; }
29+
def I6400AGEN : ProcResource<1> { let BufferSize = 0; }
3030
def I6400IssueLSU : ProcResource<1> { let Super = I6400AGEN; }
3131
def I6400IssueALU1 : ProcResource<1> { let Super = I6400AGEN; }
3232

33-
def I6400WriteLSUStore : SchedWriteRes<[I6400IssueLSU]> { let Latency = 1; }
33+
def I6400WriteLSUStore : SchedWriteRes<[I6400IssueLSU]>;
3434
def I6400WriteLSUStore2 : SchedWriteRes<[I6400IssueLSU]> {
3535
let Latency = 8;
3636
let ReleaseAtCycles = [5];
3737
}
3838
def I6400WriteLSULoad : SchedWriteRes<[I6400IssueLSU]> { let Latency = 3; }
39-
def I6400WriteLSUPref : SchedWriteRes<[I6400IssueLSU]> { let Latency = 1; }
39+
def I6400WriteLSUPref : SchedWriteRes<[I6400IssueLSU]>;
4040
def I6400WriteLSUOther : SchedWriteRes<[I6400IssueLSU]> {
4141
let Latency = 6;
4242
let ReleaseAtCycles = [5];
@@ -60,13 +60,13 @@ let SchedModel = MipsI6400Model in {
6060

6161
// CONTROL Pipelines
6262
// =================
63-
def I6400CTRL : ProcResource<1> { let BufferSize = 16; }
63+
def I6400CTRL : ProcResource<1> { let BufferSize = 0; }
6464
def I6400IssueCTU : ProcResource<1> { let Super = I6400CTRL; }
6565
def I6400IssueALU0 : ProcResource<1> { let Super = I6400CTRL; }
6666

67-
def I6400WriteALU0 : SchedWriteRes<[I6400IssueALU0]> { let Latency = 1; }
68-
def I6400WriteALU1 : SchedWriteRes<[I6400IssueALU1]> { let Latency = 1; }
69-
def I6400WriteCTU : SchedWriteRes<[I6400IssueCTU]> { let Latency = 1; }
67+
def I6400WriteALU0 : SchedWriteRes<[I6400IssueALU0]>;
68+
def I6400WriteALU1 : SchedWriteRes<[I6400IssueALU1]>;
69+
def I6400WriteCTU : SchedWriteRes<[I6400IssueCTU]>;
7070

7171
// CTU pipelines
7272
// =============
@@ -92,9 +92,7 @@ let SchedModel = MipsI6400Model in {
9292
// Either ALU0 or ALU1 pipelines
9393
// =============================
9494
def I6400IssueEitherALU : ProcResGroup<[I6400IssueALU0, I6400IssueALU1]>;
95-
def I6400WriteEitherALU : SchedWriteRes<[I6400IssueEitherALU]> {
96-
let Latency = 1;
97-
}
95+
def I6400WriteEitherALU : SchedWriteRes<[I6400IssueEitherALU]>;
9896

9997
def : InstRW<[I6400WriteEitherALU],
10098
(instrs ADD, ADDiu, ADDIUPC, ADDu, ALIGN, ALUIPC, AND, ANDi, AUI,
@@ -134,13 +132,13 @@ let SchedModel = MipsI6400Model in {
134132

135133
// FPU pipelines
136134
// =============
137-
def I6400FPU : ProcResource<3> { let BufferSize = 16; }
135+
def I6400FPU : ProcResource<3> { let BufferSize = 0; }
138136
def I6400FPUShort : ProcResource<1> { let Super = I6400FPU; }
139137
def I6400FPULong : ProcResource<1> { let Super = I6400FPU; }
140138
def I6400FPUApu : ProcResource<1>;
141139
def I6400FPUFloatL : ProcResource<1>;
142140

143-
def I6400FPUFabs : SchedWriteRes<[I6400FPUShort]> { let Latency = 1; }
141+
def I6400FPUFabs : SchedWriteRes<[I6400FPUShort]>;
144142
def : InstRW<[I6400FPUFabs], (instrs FABS_S, FNEG_S, FMOV_S,
145143
FMOV_D32, FMOV_D64,
146144
FNEG_D32, FNEG_D64, CLASS_S, CLASS_D)>;
@@ -245,7 +243,6 @@ let SchedModel = MipsI6400Model in {
245243
SHF_H, SHF_W)>;
246244

247245
def I6400MSAShortLogic : SchedWriteRes<[I6400FPUShort]> {
248-
let Latency = 1;
249246
let ReleaseAtCycles = [2];
250247
}
251248
def : InstRW<[I6400MSAShortLogic],
@@ -268,7 +265,7 @@ let SchedModel = MipsI6400Model in {
268265
def : InstRW<[I6400MSAShortLogic], (instregex "^SPLAT_(B|H|W|D)$")>;
269266
def : InstRW<[I6400MSAShortLogic], (instregex "^SPLATI_(B|H|W|D)$")>;
270267

271-
def I6400MSAShortLogic4 : SchedWriteRes<[I6400FPUShort]> { let Latency = 1; }
268+
def I6400MSAShortLogic4 : SchedWriteRes<[I6400FPUShort]>;
272269
def : InstRW<[I6400MSAShortLogic4],
273270
(instrs CTCMSA, CFCMSA, COPY_S_B, COPY_S_H, COPY_S_W, COPY_S_D,
274271
COPY_U_B, COPY_U_H, COPY_U_W, BNZ_B, BNZ_H, BNZ_W, BNZ_D,
@@ -281,7 +278,6 @@ let SchedModel = MipsI6400Model in {
281278
def : InstRW<[I6400MSAMove], (instrs LD_B, LD_H, LD_W, LD_D)>;
282279

283280
def I6400MSAMove2 : SchedWriteRes<[I6400FPUShort]> {
284-
let Latency = 1;
285281
let ReleaseAtCycles = [2];
286282
}
287283
def : InstRW<[I6400MSAMove2], (instrs LDI_B, LDI_H, LDI_W, LDI_D, MOVE_V)>;
@@ -343,7 +339,6 @@ let SchedModel = MipsI6400Model in {
343339
CEIL_W_D32, CEIL_W_D64)>;
344340

345341
def I6400MSALongLogic1 : SchedWriteRes<[I6400FPULong]> {
346-
let Latency = 1;
347342
let ReleaseAtCycles = [2];
348343
}
349344
def : InstRW<[I6400MSALongLogic1], (instrs BMZ_V, BMZI_B, BMNZ_V, BMNZI_B,
@@ -439,7 +434,7 @@ let SchedModel = MipsI6400Model in {
439434
// attach it to the Atomic2OpsPostRA, AtomicCmpSwapPostRA, ...
440435
// classes. Then just define resources for the `WriteAtomic` in each
441436
// machine models.
442-
def I6400Atomic : ProcResource<1> { let BufferSize = 1; }
437+
def I6400Atomic : ProcResource<1> { let BufferSize = 0; }
443438
def I6400WriteAtomic : SchedWriteRes<[I6400Atomic]> { let Latency = 2; }
444439

445440
def : InstRW<[I6400WriteAtomic],

‎llvm/test/tools/llvm-mca/Mips/i6400.s‎

Lines changed: 17 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ i6400:
1919

2020
# CHECK: Iterations: 1
2121
# CHECK-NEXT: Instructions: 7
22-
# CHECK-NEXT: Total Cycles: 41
22+
# CHECK-NEXT: Total Cycles: 42
2323
# CHECK-NEXT: Total uOps: 7
2424

2525
# CHECK: Dispatch Width: 2
@@ -77,15 +77,14 @@ i6400:
7777

7878
# CHECK: Timeline view:
7979
# CHECK-NEXT: 0123456789 0123456789
80-
# CHECK-NEXT: Index 0123456789 0123456789 0
81-
82-
# CHECK: [0,0] DeeeER . . . . . . . lw $1, 0($sp)
83-
# CHECK-NEXT: [0,1] D=eeeER . . . . . . . lw $2, 8($sp)
84-
# CHECK-NEXT: [0,2] .D==eER . . . . . . . move $3, $1
85-
# CHECK-NEXT: [0,3] .D===eeeeER . . . . . . mul $3, $2, $3
86-
# CHECK-NEXT: [0,4] . D======eER . . . . . . sw $3, 8($sp)
87-
# CHECK-NEXT: [0,5] . D===eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER. div $2, $1
88-
# CHECK-NEXT: [0,6] . D==================================eER sw $2, 0($sp)
80+
# CHECK-NEXT: Index 0123456789 0123456789 01
81+
# CHECK: [0,0] DeeE . . . . . . . .. lw $1, 0($sp)
82+
# CHECK-NEXT: [0,1] .DeeE. . . . . . . .. lw $2, 8($sp)
83+
# CHECK-NEXT: [0,2] . DE. . . . . . . .. move $3, $1
84+
# CHECK-NEXT: [0,3] . DeeeE . . . . . . .. mul $3, $2, $3
85+
# CHECK-NEXT: [0,4] . . DE. . . . . . .. sw $3, 8($sp)
86+
# CHECK-NEXT: [0,5] . . DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE. div $2, $1
87+
# CHECK-NEXT: [0,6] . . . . . . . . DE sw $2, 0($sp)
8988

9089
# CHECK: Average Wait times (based on the timeline view):
9190
# CHECK-NEXT: [0]: Executions
@@ -94,12 +93,12 @@ i6400:
9493
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
9594

9695
# CHECK: [0] [1] [2] [3]
97-
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 lw $1, 0($sp)
98-
# CHECK-NEXT: 1. 1 2.0 2.0 0.0 lw $2, 8($sp)
99-
# CHECK-NEXT: 2. 1 3.0 0.0 0.0 move $3, $1
100-
# CHECK-NEXT: 3. 1 4.0 0.0 0.0 mul $3, $2, $3
101-
# CHECK-NEXT: 4. 1 7.0 0.0 0.0 sw $3, 8($sp)
102-
# CHECK-NEXT: 5. 1 4.0 1.0 0.0 div $2, $1
103-
# CHECK-NEXT: 6. 1 35.0 0.0 0.0 sw $2, 0($sp)
104-
# CHECK-NEXT: 1 8.0 0.6 0.0 <total>
96+
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 lw $1, 0($sp)
97+
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 lw $2, 8($sp)
98+
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 move $3, $1
99+
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 mul $3, $2, $3
100+
# CHECK-NEXT: 4. 1 0.0 0.0 0.0 sw $3, 8($sp)
101+
# CHECK-NEXT: 5. 1 0.0 0.0 0.0 div $2, $1
102+
# CHECK-NEXT: 6. 1 0.0 0.0 0.0 sw $2, 0($sp)
103+
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
105104

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