[WIP][RISC-V] prototyping intrinsic support for Zvbc32e and Zvkgs #128243
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* Adding Zvbc32e / Zvkgs support in extension declarations * tablegen definitions for Zvbc32e * Adding RVV_REQ_Zvkgs definition [Zvbc32e/Zvkgs] introducing some changes required for fast track vector crypto extensions more changes Adding Zvkgs instrinsics Adding zvkgs + zvbc32e in RISC-V supported extensions (RISCVISAInfo.cpp) Adding zvkgs + zvbc32e in RISC-V supported extensions (RISCVISAInfo.cpp)
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This PR is built has a porting to main of a branch which was originally created on top of llvm 18.1.8 tag (the top tag in riscv-gnu-toolchain when this effort was started). It looks like a few changes (including opcodes for the Zvkgs) did not make it properly to the port. https://github.com/nibrunie/llvm-project/commits/riscv-zvbc32e-zvkgs-proto_from_llvmorg-18.1.8/ |
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Actually, it looks like most of the support may have already been added as part of a80a90e |
nibrunieAtSi5
changed the title
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This PR introduces support for a couple of vector crypto extensions under going the specification process at RVIA. Those extensions, Zvbc32e and Zvkgs, are undergoing a fast track process which is tracked by riscv/riscv-isa-manual#1306 and https://lf-riscv.atlassian.net/browse/RVS-1915.
What is done as part of this PR: