[mlir][rocdl] Add more gfx12 wait intrinsics #149984
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@llvm/pr-subscribers-mlir Author: Ivan Butygin (Hardcode84) ChangesFull diff: https://github.com/llvm/llvm-project/pull/149984.diff 2 Files Affected:
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index 906aaca21187b..eb9745a1b0425 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -284,10 +284,28 @@ def ROCDL_BarrierWaitOp : ROCDL_ConcreteNonMemIntrOp<"s.barrier.wait", [], 0, [0
let assemblyFormat = "$id attr-dict";
}
-def ROCDL_WaitDscntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.dscnt", [], 0, [0], ["id"]>,
- Arguments<(ins I16Attr:$id)> {
+def ROCDL_WaitDscntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.dscnt", [], 0, [0], ["count"]>,
+ Arguments<(ins I16Attr:$count)> {
let results = (outs);
- let assemblyFormat = "$id attr-dict";
+ let assemblyFormat = "$count attr-dict";
+}
+
+def ROCDL_WaitLoadcntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.loadcnt", [], 0, [0], ["count"]>,
+ Arguments<(ins I16Attr:$count)> {
+ let results = (outs);
+ let assemblyFormat = "$count attr-dict";
+}
+
+def ROCDL_WaitStorecntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.storecnt", [], 0, [0], ["count"]>,
+ Arguments<(ins I16Attr:$count)> {
+ let results = (outs);
+ let assemblyFormat = "$count attr-dict";
+}
+
+def ROCDL_WaitExpcntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.expcnt", [], 0, [0], ["count"]>,
+ Arguments<(ins I16Attr:$count)> {
+ let results = (outs);
+ let assemblyFormat = "$count attr-dict";
}
def ROCDL_SetPrioOp : ROCDL_ConcreteNonMemIntrOp<"s.setprio", [], 0, [0], ["priority"]>,
diff --git a/mlir/test/Target/LLVMIR/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir
index 0742eb3620a7c..740990a6e589b 100644
--- a/mlir/test/Target/LLVMIR/rocdl.mlir
+++ b/mlir/test/Target/LLVMIR/rocdl.mlir
@@ -196,6 +196,27 @@ llvm.func @rocdl.s.wait.dscnt() {
llvm.return
}
+llvm.func @rocdl.s.wait.loadcnt() {
+ // CHECK-LABEL: rocdl.s.wait.loadcnt
+ // CHECK-NEXT: call void @llvm.amdgcn.s.wait.loadcnt(i16 0)
+ rocdl.s.wait.loadcnt 0
+ llvm.return
+}
+
+llvm.func @rocdl.s.wait.storecnt() {
+ // CHECK-LABEL: rocdl.s.wait.storecnt
+ // CHECK-NEXT: call void @llvm.amdgcn.s.wait.storecnt(i16 0)
+ rocdl.s.wait.storecnt 0
+ llvm.return
+}
+
+llvm.func @rocdl.s.wait.expcnt() {
+ // CHECK-LABEL: rocdl.s.wait.expcnt
+ // CHECK-NEXT: call void @llvm.amdgcn.s.wait.expcnt(i16 0)
+ rocdl.s.wait.expcnt 0
+ llvm.return
+}
+
llvm.func @rocdl.setprio() {
// CHECK: call void @llvm.amdgcn.s.setprio(i16 0)
rocdl.s.setprio 0
|
Member
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@llvm/pr-subscribers-mlir-llvm Author: Ivan Butygin (Hardcode84) ChangesFull diff: https://github.com/llvm/llvm-project/pull/149984.diff 2 Files Affected:
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index 906aaca21187b..eb9745a1b0425 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -284,10 +284,28 @@ def ROCDL_BarrierWaitOp : ROCDL_ConcreteNonMemIntrOp<"s.barrier.wait", [], 0, [0
let assemblyFormat = "$id attr-dict";
}
-def ROCDL_WaitDscntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.dscnt", [], 0, [0], ["id"]>,
- Arguments<(ins I16Attr:$id)> {
+def ROCDL_WaitDscntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.dscnt", [], 0, [0], ["count"]>,
+ Arguments<(ins I16Attr:$count)> {
let results = (outs);
- let assemblyFormat = "$id attr-dict";
+ let assemblyFormat = "$count attr-dict";
+}
+
+def ROCDL_WaitLoadcntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.loadcnt", [], 0, [0], ["count"]>,
+ Arguments<(ins I16Attr:$count)> {
+ let results = (outs);
+ let assemblyFormat = "$count attr-dict";
+}
+
+def ROCDL_WaitStorecntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.storecnt", [], 0, [0], ["count"]>,
+ Arguments<(ins I16Attr:$count)> {
+ let results = (outs);
+ let assemblyFormat = "$count attr-dict";
+}
+
+def ROCDL_WaitExpcntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.expcnt", [], 0, [0], ["count"]>,
+ Arguments<(ins I16Attr:$count)> {
+ let results = (outs);
+ let assemblyFormat = "$count attr-dict";
}
def ROCDL_SetPrioOp : ROCDL_ConcreteNonMemIntrOp<"s.setprio", [], 0, [0], ["priority"]>,
diff --git a/mlir/test/Target/LLVMIR/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir
index 0742eb3620a7c..740990a6e589b 100644
--- a/mlir/test/Target/LLVMIR/rocdl.mlir
+++ b/mlir/test/Target/LLVMIR/rocdl.mlir
@@ -196,6 +196,27 @@ llvm.func @rocdl.s.wait.dscnt() {
llvm.return
}
+llvm.func @rocdl.s.wait.loadcnt() {
+ // CHECK-LABEL: rocdl.s.wait.loadcnt
+ // CHECK-NEXT: call void @llvm.amdgcn.s.wait.loadcnt(i16 0)
+ rocdl.s.wait.loadcnt 0
+ llvm.return
+}
+
+llvm.func @rocdl.s.wait.storecnt() {
+ // CHECK-LABEL: rocdl.s.wait.storecnt
+ // CHECK-NEXT: call void @llvm.amdgcn.s.wait.storecnt(i16 0)
+ rocdl.s.wait.storecnt 0
+ llvm.return
+}
+
+llvm.func @rocdl.s.wait.expcnt() {
+ // CHECK-LABEL: rocdl.s.wait.expcnt
+ // CHECK-NEXT: call void @llvm.amdgcn.s.wait.expcnt(i16 0)
+ rocdl.s.wait.expcnt 0
+ llvm.return
+}
+
llvm.func @rocdl.setprio() {
// CHECK: call void @llvm.amdgcn.s.setprio(i16 0)
rocdl.s.setprio 0
|
tgymnich
approved these changes
Jul 22, 2025
kuhar
approved these changes
Jul 22, 2025
krzysz00
approved these changes
Jul 22, 2025
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krzysz00
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krzysz00
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There should also be a test in test/Dialect/LLVMIR/rocdl.mlir just to verify parsing/printing. Otherwise, approved.
kuhar
reviewed
Jul 22, 2025
kuhar
approved these changes
Jul 22, 2025
mahesh-attarde
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Jul 28, 2025
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