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Merged
merged 1 commit into from
Sep 16, 2025
Merged

[LoongArch][NFC] Add tests for vector type orn/andn #158525

merged 1 commit into from
Sep 16, 2025

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@zhaoqi5 zhaoqi5 commented Sep 15, 2025

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llvmbot commented Sep 15, 2025

@llvm/pr-subscribers-backend-loongarch

Author: ZhaoQi (zhaoqi5)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/158525.diff

4 Files Affected:

  • (added) llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll (+78)
  • (added) llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll (+78)
  • (added) llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll (+78)
  • (added) llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll (+78)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll
new file mode 100644
index 0000000000000..ea3b6144805ae
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/andn.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define void @andn_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvld $xr0, $a1, 0
+; CHECK-NEXT:    xvld $xr1, $a2, 0
+; CHECK-NEXT:    xvxori.b $xr0, $xr0, 255
+; CHECK-NEXT:    xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT:    xvst $xr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <32 x i8>, ptr %a0
+  %v1 = load <32 x i8>, ptr %a1
+  %v2 = xor <32 x i8> %v0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %v3 = and <32 x i8> %v2, %v1
+  store <32 x i8> %v3, ptr %res
+  ret void
+}
+
+define void @andn_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvld $xr0, $a1, 0
+; CHECK-NEXT:    xvld $xr1, $a2, 0
+; CHECK-NEXT:    xvrepli.b $xr2, -1
+; CHECK-NEXT:    xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT:    xvst $xr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <16 x i16>, ptr %a0
+  %v1 = load <16 x i16>, ptr %a1
+  %v2 = xor <16 x i16> %v0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %v3 = and <16 x i16> %v2, %v1
+  store <16 x i16> %v3, ptr %res
+  ret void
+}
+
+define void @andn_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvld $xr0, $a1, 0
+; CHECK-NEXT:    xvld $xr1, $a2, 0
+; CHECK-NEXT:    xvrepli.b $xr2, -1
+; CHECK-NEXT:    xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT:    xvst $xr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <8 x i32>, ptr %a0
+  %v1 = load <8 x i32>, ptr %a1
+  %v2 = xor <8 x i32> %v0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+  %v3 = and <8 x i32> %v2, %v1
+  store <8 x i32> %v3, ptr %res
+  ret void
+}
+
+define void @andn_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvld $xr0, $a1, 0
+; CHECK-NEXT:    xvld $xr1, $a2, 0
+; CHECK-NEXT:    xvrepli.b $xr2, -1
+; CHECK-NEXT:    xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT:    xvst $xr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <4 x i64>, ptr %a0
+  %v1 = load <4 x i64>, ptr %a1
+  %v2 = xor <4 x i64> %v0, <i64 -1, i64 -1, i64 -1, i64 -1>
+  %v3 = and <4 x i64> %v2, %v1
+  store <4 x i64> %v3, ptr %res
+  ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll
new file mode 100644
index 0000000000000..5115fa880271d
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/orn.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define void @orn_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvld $xr0, $a2, 0
+; CHECK-NEXT:    xvld $xr1, $a1, 0
+; CHECK-NEXT:    xvxori.b $xr0, $xr0, 255
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    xvst $xr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <32 x i8>, ptr %a0
+  %v1 = load <32 x i8>, ptr %a1
+  %v2 = xor <32 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %v3 = or <32 x i8> %v0, %v2
+  store <32 x i8> %v3, ptr %res
+  ret void
+}
+
+define void @orn_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvld $xr0, $a2, 0
+; CHECK-NEXT:    xvld $xr1, $a1, 0
+; CHECK-NEXT:    xvrepli.b $xr2, -1
+; CHECK-NEXT:    xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    xvst $xr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <16 x i16>, ptr %a0
+  %v1 = load <16 x i16>, ptr %a1
+  %v2 = xor <16 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %v3 = or <16 x i16> %v0, %v2
+  store <16 x i16> %v3, ptr %res
+  ret void
+}
+
+define void @orn_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvld $xr0, $a2, 0
+; CHECK-NEXT:    xvld $xr1, $a1, 0
+; CHECK-NEXT:    xvrepli.b $xr2, -1
+; CHECK-NEXT:    xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    xvst $xr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <8 x i32>, ptr %a0
+  %v1 = load <8 x i32>, ptr %a1
+  %v2 = xor <8 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+  %v3 = or <8 x i32> %v0, %v2
+  store <8 x i32> %v3, ptr %res
+  ret void
+}
+
+define void @orn_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvld $xr0, $a2, 0
+; CHECK-NEXT:    xvld $xr1, $a1, 0
+; CHECK-NEXT:    xvrepli.b $xr2, -1
+; CHECK-NEXT:    xvxor.v $xr0, $xr0, $xr2
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    xvst $xr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <4 x i64>, ptr %a0
+  %v1 = load <4 x i64>, ptr %a1
+  %v2 = xor <4 x i64> %v1, <i64 -1, i64 -1, i64 -1, i64 -1>
+  %v3 = or <4 x i64> %v0, %v2
+  store <4 x i64> %v3, ptr %res
+  ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll
new file mode 100644
index 0000000000000..4b6a77919659b
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/andn.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define void @andn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a1, 0
+; CHECK-NEXT:    vld $vr1, $a2, 0
+; CHECK-NEXT:    vxori.b $vr0, $vr0, 255
+; CHECK-NEXT:    vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT:    vst $vr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <16 x i8>, ptr %a0
+  %v1 = load <16 x i8>, ptr %a1
+  %v2 = xor <16 x i8> %v0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %v3 = and <16 x i8> %v2, %v1
+  store <16 x i8> %v3, ptr %res
+  ret void
+}
+
+define void @andn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a1, 0
+; CHECK-NEXT:    vld $vr1, $a2, 0
+; CHECK-NEXT:    vrepli.b $vr2, -1
+; CHECK-NEXT:    vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT:    vst $vr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <8 x i16>, ptr %a0
+  %v1 = load <8 x i16>, ptr %a1
+  %v2 = xor <8 x i16> %v0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %v3 = and <8 x i16> %v2, %v1
+  store <8 x i16> %v3, ptr %res
+  ret void
+}
+
+define void @andn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a1, 0
+; CHECK-NEXT:    vld $vr1, $a2, 0
+; CHECK-NEXT:    vrepli.b $vr2, -1
+; CHECK-NEXT:    vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT:    vst $vr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <4 x i32>, ptr %a0
+  %v1 = load <4 x i32>, ptr %a1
+  %v2 = xor <4 x i32> %v0, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %v3 = and <4 x i32> %v2, %v1
+  store <4 x i32> %v3, ptr %res
+  ret void
+}
+
+define void @andn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: andn_v2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a1, 0
+; CHECK-NEXT:    vld $vr1, $a2, 0
+; CHECK-NEXT:    vrepli.b $vr2, -1
+; CHECK-NEXT:    vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT:    vst $vr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <2 x i64>, ptr %a0
+  %v1 = load <2 x i64>, ptr %a1
+  %v2 = xor <2 x i64> %v0, <i64 -1, i64 -1>
+  %v3 = and <2 x i64> %v2, %v1
+  store <2 x i64> %v3, ptr %res
+  ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll
new file mode 100644
index 0000000000000..524dfd616fa3b
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define void @orn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a2, 0
+; CHECK-NEXT:    vld $vr1, $a1, 0
+; CHECK-NEXT:    vxori.b $vr0, $vr0, 255
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    vst $vr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <16 x i8>, ptr %a0
+  %v1 = load <16 x i8>, ptr %a1
+  %v2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %v3 = or <16 x i8> %v0, %v2
+  store <16 x i8> %v3, ptr %res
+  ret void
+}
+
+define void @orn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a2, 0
+; CHECK-NEXT:    vld $vr1, $a1, 0
+; CHECK-NEXT:    vrepli.b $vr2, -1
+; CHECK-NEXT:    vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    vst $vr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <8 x i16>, ptr %a0
+  %v1 = load <8 x i16>, ptr %a1
+  %v2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %v3 = or <8 x i16> %v0, %v2
+  store <8 x i16> %v3, ptr %res
+  ret void
+}
+
+define void @orn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a2, 0
+; CHECK-NEXT:    vld $vr1, $a1, 0
+; CHECK-NEXT:    vrepli.b $vr2, -1
+; CHECK-NEXT:    vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    vst $vr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <4 x i32>, ptr %a0
+  %v1 = load <4 x i32>, ptr %a1
+  %v2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %v3 = or <4 x i32> %v0, %v2
+  store <4 x i32> %v3, ptr %res
+  ret void
+}
+
+define void @orn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
+; CHECK-LABEL: orn_v2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a2, 0
+; CHECK-NEXT:    vld $vr1, $a1, 0
+; CHECK-NEXT:    vrepli.b $vr2, -1
+; CHECK-NEXT:    vxor.v $vr0, $vr0, $vr2
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    vst $vr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %v0 = load <2 x i64>, ptr %a0
+  %v1 = load <2 x i64>, ptr %a1
+  %v2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
+  %v3 = or <2 x i64> %v0, %v2
+  store <2 x i64> %v3, ptr %res
+  ret void
+}

@zhaoqi5 zhaoqi5 merged commit dfa5bbe into main Sep 16, 2025
13 checks passed
@zhaoqi5 zhaoqi5 deleted the users/zhaoqi5/test-andn-orn branch September 16, 2025 01:56
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llvm-ci commented Sep 16, 2025

LLVM Buildbot has detected a new failure on builder lldb-aarch64-ubuntu running on linaro-lldb-aarch64-ubuntu while building llvm at step 6 "test".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/59/builds/24240

Here is the relevant piece of the build log for the reference 
Step 6 (test) failure: build (failure)
...
PASS: lldb-api :: functionalities/postmortem/elf-core/expr/TestExpr.py (571 of 2321)
PASS: lldb-api :: functionalities/postmortem/elf-core/gcore/TestGCore.py (572 of 2321)
PASS: lldb-api :: functionalities/postmortem/elf-core/thread_crash/TestLinuxCoreThreads.py (573 of 2321)
PASS: lldb-api :: functionalities/plugins/python_os_plugin/stepping_plugin_threads/TestOSPluginStepping.py (574 of 2321)
PASS: lldb-api :: functionalities/postmortem/minidump/TestMiniDump.py (575 of 2321)
PASS: lldb-api :: functionalities/postmortem/minidump-new/TestMiniDumpNew.py (576 of 2321)
PASS: lldb-api :: functionalities/postmortem/minidump-new/TestMiniDumpUUID.py (577 of 2321)
UNSUPPORTED: lldb-api :: functionalities/pre_run_dylibs/TestPreRunDylibs.py (578 of 2321)
PASS: lldb-api :: functionalities/postmortem/wow64_minidump/TestWow64MiniDump.py (579 of 2321)
UNRESOLVED: lldb-api :: functionalities/postmortem/netbsd-core/TestNetBSDCore.py (580 of 2321)
******************** TEST 'lldb-api :: functionalities/postmortem/netbsd-core/TestNetBSDCore.py' FAILED ********************
Script:
--
/usr/bin/python3.10 /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/llvm-project/lldb/test/API/dotest.py -u CXXFLAGS -u CFLAGS --env LLVM_LIBS_DIR=/home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/./lib --env LLVM_INCLUDE_DIR=/home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/include --env LLVM_TOOLS_DIR=/home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/./bin --arch aarch64 --build-dir /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/lldb-test-build.noindex --lldb-module-cache-dir /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/lldb-test-build.noindex/module-cache-lldb/lldb-api --clang-module-cache-dir /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/lldb-test-build.noindex/module-cache-clang/lldb-api --executable /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/./bin/lldb --compiler /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/./bin/clang --dsymutil /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/./bin/dsymutil --make /usr/bin/gmake --llvm-tools-dir /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/./bin --lldb-obj-root /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/tools/lldb --lldb-libs-dir /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/./lib --cmake-build-type Release /home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/llvm-project/lldb/test/API/functionalities/postmortem/netbsd-core -p TestNetBSDCore.py
--
Exit Code: -11

Command Output (stdout):
--
lldb version 22.0.0git (https://github.com/llvm/llvm-project.git revision dfa5bbeafaff2bbb211cde2980cc5f29906d8fac)
  clang revision dfa5bbeafaff2bbb211cde2980cc5f29906d8fac
  llvm revision dfa5bbeafaff2bbb211cde2980cc5f29906d8fac
Skipping the following test categories: ['libc++', 'msvcstl', 'dsym', 'gmodules', 'debugserver', 'objc']

--
Command Output (stderr):
--
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
 #0 0x0000e01122d93200 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) Signals.cpp:0:0
 #1 0x0000e01122d90d1c llvm::sys::RunSignalHandlers() Signals.cpp:0:0
 #2 0x0000e01122d9401c SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
 #3 0x0000e01129a1c8f8 (linux-vdso.so.1+0x8f8)
 #4 0x0000e0112283eb60 std::_Rb_tree<int, std::pair<int const, lldb_private::UnixSignals::Signal>, std::_Select1st<std::pair<int const, lldb_private::UnixSignals::Signal> >, std::less<int>, std::allocator<std::pair<int const, lldb_private::UnixSignals::Signal> > >::_M_erase(std::_Rb_tree_node<std::pair<int const, lldb_private::UnixSignals::Signal> >*) UnixSignals.cpp:0:0
 #5 0x0000e0112283eb6c std::_Rb_tree<int, std::pair<int const, lldb_private::UnixSignals::Signal>, std::_Select1st<std::pair<int const, lldb_private::UnixSignals::Signal> >, std::less<int>, std::allocator<std::pair<int const, lldb_private::UnixSignals::Signal> > >::_M_erase(std::_Rb_tree_node<std::pair<int const, lldb_private::UnixSignals::Signal> >*) UnixSignals.cpp:0:0
 #6 0x0000e0112283eb6c std::_Rb_tree<int, std::pair<int const, lldb_private::UnixSignals::Signal>, std::_Select1st<std::pair<int const, lldb_private::UnixSignals::Signal> >, std::less<int>, std::allocator<std::pair<int const, lldb_private::UnixSignals::Signal> > >::_M_erase(std::_Rb_tree_node<std::pair<int const, lldb_private::UnixSignals::Signal> >*) UnixSignals.cpp:0:0
 #7 0x0000e0112283eb6c std::_Rb_tree<int, std::pair<int const, lldb_private::UnixSignals::Signal>, std::_Select1st<std::pair<int const, lldb_private::UnixSignals::Signal> >, std::less<int>, std::allocator<std::pair<int const, lldb_private::UnixSignals::Signal> > >::_M_erase(std::_Rb_tree_node<std::pair<int const, lldb_private::UnixSignals::Signal> >*) UnixSignals.cpp:0:0
 #8 0x0000e0112283eb6c std::_Rb_tree<int, std::pair<int const, lldb_private::UnixSignals::Signal>, std::_Select1st<std::pair<int const, lldb_private::UnixSignals::Signal> >, std::less<int>, std::allocator<std::pair<int const, lldb_private::UnixSignals::Signal> > >::_M_erase(std::_Rb_tree_node<std::pair<int const, lldb_private::UnixSignals::Signal> >*) UnixSignals.cpp:0:0
 #9 0x0000e01122783508 lldb_private::Process::SetUnixSignals(std::shared_ptr<lldb_private::UnixSignals>&&) Process.cpp:0:0
#10 0x0000e01122b88e6c ProcessElfCore::Clear() ProcessElfCore.cpp:0:0
#11 0x0000e01122b88bbc ProcessElfCore::~ProcessElfCore() ProcessElfCore.cpp:0:0
#12 0x0000e011227d55e0 lldb_private::Target::DeleteCurrentProcess() Target.cpp:0:0
#13 0x0000e011227d756c lldb_private::Target::Destroy() Target.cpp:0:0
#14 0x0000e01122379e4c lldb::SBDebugger::DeleteTarget(lldb::SBTarget&) (/home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/build/local/lib/python3.10/dist-packages/lldb/_lldb.cpython-310-aarch64-linux-gnu.so+0x5789e4c)
#15 0x0000e011224b5860 _wrap_SBDebugger_DeleteTarget(_object*, _object*) LLDBWrapPython.cpp:0:0
#16 0x0000bbf819f53c64 (/usr/bin/python3.10+0x103c64)
#17 0x0000bbf819f4a240 _PyObject_MakeTpCall (/usr/bin/python3.10+0xfa240)
#18 0x0000bbf819f41518 _PyEval_EvalFrameDefault (/usr/bin/python3.10+0xf1518)
#19 0x0000bbf819f548c8 _PyFunction_Vectorcall (/usr/bin/python3.10+0x1048c8)
#20 0x0000bbf819f3c9e0 _PyEval_EvalFrameDefault (/usr/bin/python3.10+0xec9e0)

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@zhaoqi5 @llvmbot @llvm-ci