[PowerPC] Implement vsx rotate left word instr

[lei137]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-powerpc

Author: Lei Huang (lei137)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/160754.diff

4 Files Affected:

• (modified) llvm/lib/Target/PowerPC/PPCInstrFuture.td (+3)
• (modified) llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt (+3)
• (modified) llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt (+3)
• (modified) llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s (+4)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 08d633f962d93..17220415b8869 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -294,6 +294,9 @@ let Predicates = [HasVSX, IsISAFuture] in {
                               "xvmulhuw $XT, $XA, $XB", []>;
   def XVMULHUH: XX3Form_XTAB6<60, 122, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                               "xvmulhuh $XT, $XA, $XB", []>;
+
+  def XVRLW: XX3Form_XTAB6<60, 184, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                              "xvrlw $XT, $XA, $XB", []>;
 }
 
 //---------------------------- Anonymous Patterns ----------------------------//
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index a34e7f54c2234..7a76cf9242403 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -273,3 +273,6 @@
 
 #CHECK: xvmulhuh  4, 5, 7
 0xf0,0x85,0x3b,0xd0
+
+#CHECK: xvrlw 34, 15, 16
+0xf0,0x4f,0x85,0xc1
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 9cefe2451b0e3..c98d71650a3f6 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -267,3 +267,6 @@
 
 #CHECK: xvmulhuh  4, 5, 7
 0xd0,0x3b,0x85,0xf0
+
+#CHECK: xvrlw 34, 15, 16
+0xc1,0x85,0x4f,0xf0
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index f01d6fa697d89..44c275da6328f 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -386,3 +386,7 @@
            xvmulhuh 4, 5, 7
 #CHECK-BE: xvmulhuh 4, 5, 7              # encoding: [0xf0,0x85,0x3b,0xd0]
 #CHECK-LE: xvmulhuh 4, 5, 7              # encoding: [0xd0,0x3b,0x85,0xf0]
+
+           xvrlw 34, 15, 16
+#CHECK-BE: xvrlw 34, 15, 16              # encoding: [0xf0,0x4f,0x85,0xc1]
+#CHECK-LE: xvrlw 34, 15, 16              # encoding: [0xc1,0x85,0x4f,0xf0]

[lei137]

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