[Mips] Fix mcpu flag with i6400/i6500 #161330

ArielCPU · 2025-09-30T07:38:18Z

The compiler is missing cases where it checks mips64r6 but not i6400/i6500 causing wrong defines to be generated

github-actions · 2025-09-30T07:38:40Z

Thank you for submitting a Pull Request (PR) to the LLVM Project!

This PR will be automatically labeled and the relevant teams will be notified.

If you wish to, you can add reviewers by using the "Reviewers" section on this page.

If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using @ followed by their GitHub username.

If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers.

If you have further questions, they may be answered by the LLVM GitHub User Guide.

You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums.

llvmbot · 2025-09-30T07:39:13Z

@llvm/pr-subscribers-clang

@llvm/pr-subscribers-backend-mips

Author: None (ArielCPU)

Changes

The compiler is missing cases where it checks mips64r6 but not i6400/i6500 causing wrong defines to be generated

Full diff: https://github.com/llvm/llvm-project/pull/161330.diff

4 Files Affected:

(modified) clang/lib/Basic/Targets/Mips.cpp (+2-2)
(modified) clang/lib/Basic/Targets/Mips.h (+1-1)
(modified) clang/lib/Driver/ToolChains/Arch/Mips.cpp (+2)
(modified) clang/test/Preprocessor/init-mips.c (+22)

diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 34837cc363a37..c806c5f7671d0 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -72,7 +72,7 @@ unsigned MipsTargetInfo::getISARev() const {
       .Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2)
       .Cases("mips32r3", "mips64r3", 3)
       .Cases("mips32r5", "mips64r5", "p5600", 5)
-      .Cases("mips32r6", "mips64r6", 6)
+      .Cases("mips32r6", "mips64r6", "i6400", "i6500", 6)
       .Default(0);
 }
 
@@ -271,7 +271,7 @@ bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
   }
   // Mips revision 6 and -mfp32 are incompatible
   if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
-      CPU == "mips64r6")) {
+      CPU == "mips64r6" || CPU == "i6400" || CPU == "i6500")) {
     Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
     return false;
   }
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index e199df32f56ee..106c4f8d637eb 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -83,7 +83,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
   }
 
   bool isIEEE754_2008Default() const {
-    return CPU == "mips32r6" || CPU == "mips64r6";
+    return CPU == "mips32r6" || CPU == "mips64r6" || CPU == "i6400" || CPU == "i6500";
   }
 
   enum FPModeEnum getDefaultFPMode() const {
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index 8787c8276721c..bac8681921877 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -442,6 +442,8 @@ bool mips::hasCompactBranches(StringRef &CPU) {
   return llvm::StringSwitch<bool>(CPU)
       .Case("mips32r6", true)
       .Case("mips64r6", true)
+      .Case("i6400", true)
+      .Case("i6500", true)
       .Default(false);
 }
 
diff --git a/clang/test/Preprocessor/init-mips.c b/clang/test/Preprocessor/init-mips.c
index 125872a001bac..c829eebdc9ec9 100644
--- a/clang/test/Preprocessor/init-mips.c
+++ b/clang/test/Preprocessor/init-mips.c
@@ -1649,6 +1649,28 @@
 // MIPS-ARCH-OCTEONP:#define __OCTEON__ 1
 // MIPS-ARCH-OCTEONP:#define __mips_isa_rev 2
 
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \
+// RUN:            -target-cpu i6400 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix MIPS-ARCH-I6400 %s
+//
+// MIPS-ARCH-I6400:#define _MIPS_ARCH "i6400"
+// MIPS-ARCH-I6400:#define _MIPS_ARCH_I6400 1
+// MIPS-ARCH-I6400:#define _MIPS_ISA _MIPS_ISA_MIPS64
+// MIPS-ARCH-I6400:#define __mips_abs2008 1
+// MIPS-ARCH-I6400:#define __mips_isa_rev 6
+// MIPS-ARCH-I6400:#define __mips_nan2008 1
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \
+// RUN:            -target-cpu i6500 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix MIPS-ARCH-I6500 %s
+//
+// MIPS-ARCH-I6500:#define _MIPS_ARCH "i6500"
+// MIPS-ARCH-I6500:#define _MIPS_ARCH_I6500 1
+// MIPS-ARCH-I6500:#define _MIPS_ISA _MIPS_ISA_MIPS64
+// MIPS-ARCH-I6500:#define __mips_abs2008 1
+// MIPS-ARCH-I6500:#define __mips_isa_rev 6
+// MIPS-ARCH-I6500:#define __mips_nan2008 1
+
 // Check MIPS float ABI macros
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding \

llvmbot · 2025-09-30T07:39:14Z

@llvm/pr-subscribers-clang-driver

Author: None (ArielCPU)

Changes

The compiler is missing cases where it checks mips64r6 but not i6400/i6500 causing wrong defines to be generated

Full diff: https://github.com/llvm/llvm-project/pull/161330.diff

4 Files Affected:

(modified) clang/lib/Basic/Targets/Mips.cpp (+2-2)
(modified) clang/lib/Basic/Targets/Mips.h (+1-1)
(modified) clang/lib/Driver/ToolChains/Arch/Mips.cpp (+2)
(modified) clang/test/Preprocessor/init-mips.c (+22)

diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 34837cc363a37..c806c5f7671d0 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -72,7 +72,7 @@ unsigned MipsTargetInfo::getISARev() const {
       .Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2)
       .Cases("mips32r3", "mips64r3", 3)
       .Cases("mips32r5", "mips64r5", "p5600", 5)
-      .Cases("mips32r6", "mips64r6", 6)
+      .Cases("mips32r6", "mips64r6", "i6400", "i6500", 6)
       .Default(0);
 }
 
@@ -271,7 +271,7 @@ bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
   }
   // Mips revision 6 and -mfp32 are incompatible
   if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
-      CPU == "mips64r6")) {
+      CPU == "mips64r6" || CPU == "i6400" || CPU == "i6500")) {
     Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
     return false;
   }
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index e199df32f56ee..106c4f8d637eb 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -83,7 +83,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
   }
 
   bool isIEEE754_2008Default() const {
-    return CPU == "mips32r6" || CPU == "mips64r6";
+    return CPU == "mips32r6" || CPU == "mips64r6" || CPU == "i6400" || CPU == "i6500";
   }
 
   enum FPModeEnum getDefaultFPMode() const {
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index 8787c8276721c..bac8681921877 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -442,6 +442,8 @@ bool mips::hasCompactBranches(StringRef &CPU) {
   return llvm::StringSwitch<bool>(CPU)
       .Case("mips32r6", true)
       .Case("mips64r6", true)
+      .Case("i6400", true)
+      .Case("i6500", true)
       .Default(false);
 }
 
diff --git a/clang/test/Preprocessor/init-mips.c b/clang/test/Preprocessor/init-mips.c
index 125872a001bac..c829eebdc9ec9 100644
--- a/clang/test/Preprocessor/init-mips.c
+++ b/clang/test/Preprocessor/init-mips.c
@@ -1649,6 +1649,28 @@
 // MIPS-ARCH-OCTEONP:#define __OCTEON__ 1
 // MIPS-ARCH-OCTEONP:#define __mips_isa_rev 2
 
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \
+// RUN:            -target-cpu i6400 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix MIPS-ARCH-I6400 %s
+//
+// MIPS-ARCH-I6400:#define _MIPS_ARCH "i6400"
+// MIPS-ARCH-I6400:#define _MIPS_ARCH_I6400 1
+// MIPS-ARCH-I6400:#define _MIPS_ISA _MIPS_ISA_MIPS64
+// MIPS-ARCH-I6400:#define __mips_abs2008 1
+// MIPS-ARCH-I6400:#define __mips_isa_rev 6
+// MIPS-ARCH-I6400:#define __mips_nan2008 1
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \
+// RUN:            -target-cpu i6500 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix MIPS-ARCH-I6500 %s
+//
+// MIPS-ARCH-I6500:#define _MIPS_ARCH "i6500"
+// MIPS-ARCH-I6500:#define _MIPS_ARCH_I6500 1
+// MIPS-ARCH-I6500:#define _MIPS_ISA _MIPS_ISA_MIPS64
+// MIPS-ARCH-I6500:#define __mips_abs2008 1
+// MIPS-ARCH-I6500:#define __mips_isa_rev 6
+// MIPS-ARCH-I6500:#define __mips_nan2008 1
+
 // Check MIPS float ABI macros
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding \

The compiler is missing cases where it checks mips64r6 but not i6400/i6500 causing wrong defines to be generated

ArielCPU · 2025-10-12T13:50:57Z

@yingopq Thanks for the approve, can you merge this PR for me?

yingopq · 2025-10-13T09:02:58Z

Is there a corresponding issue?

ArielCPU · 2025-10-13T09:27:15Z

Is there a corresponding issue?

Because I am a new member of LLVM, I cannot merge PRs

yingopq · 2025-10-13T09:30:52Z

I mean how you find this issue, is there an existed issue?

ArielCPU · 2025-10-13T09:53:51Z

I mean how you find this issue, is there an existed issue?

No, I found it while working on it, I work at Mobileye and we have these CPUs

github-actions · 2025-10-13T10:05:01Z

@ArielCPU Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR.

Please check whether problems have been caused by your change specifically, as the builds can include changes from many authors. It is not uncommon for your change to be included in a build that fails due to someone else's changes, or infrastructure issues.

How to do this, and the rest of the post-merge process, is covered in detail here.

If your change does cause a problem, it may be reverted, or you can revert it yourself. This is a normal part of LLVM development. You can fix your changes and open a new PR to merge them again.

If you don't get any reports, no action is required from you. Your changes are working as expected, well done!

The compiler is missing cases where it checks mips64r6 but not i6400/i6500 causing wrong defines to be generated

llvmbot added clang Clang issues not falling into any other category backend:MIPS clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" labels Sep 30, 2025

[Mips] Fix mcpu flag with i6400/i6500

0d63be9

The compiler is missing cases where it checks mips64r6 but not i6400/i6500 causing wrong defines to be generated

ArielCPU force-pushed the users/arielcpu/mips-i6400-i6500-fix branch from 95879ea to 0d63be9 Compare September 30, 2025 07:40

brad0 requested a review from yingopq October 8, 2025 01:48

yingopq approved these changes Oct 11, 2025

View reviewed changes

ArielCPU added 2 commits October 12, 2025 09:58

Merge branch 'main' into users/arielcpu/mips-i6400-i6500-fix

6c39322

Merge branch 'main' into users/arielcpu/mips-i6400-i6500-fix

d53174d

yingopq merged commit dd0fc25 into llvm:main Oct 13, 2025
10 checks passed

DharuniRAcharya pushed a commit to DharuniRAcharya/llvm-project that referenced this pull request Oct 13, 2025

[Mips] Fix mcpu flag with i6400/i6500 (llvm#161330)

57a3b9c

The compiler is missing cases where it checks mips64r6 but not i6400/i6500 causing wrong defines to be generated

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[Mips] Fix mcpu flag with i6400/i6500 #161330

[Mips] Fix mcpu flag with i6400/i6500 #161330

ArielCPU commented Sep 30, 2025

Uh oh!

github-actions bot commented Sep 30, 2025

Uh oh!

llvmbot commented Sep 30, 2025 •

edited

Loading

Uh oh!

llvmbot commented Sep 30, 2025

Uh oh!

ArielCPU commented Oct 12, 2025

Uh oh!

yingopq commented Oct 13, 2025

Uh oh!

ArielCPU commented Oct 13, 2025

Uh oh!

yingopq commented Oct 13, 2025 •

edited

Loading

Uh oh!

ArielCPU commented Oct 13, 2025

Uh oh!

Uh oh!

github-actions bot commented Oct 13, 2025

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

[Mips] Fix mcpu flag with i6400/i6500 #161330

[Mips] Fix mcpu flag with i6400/i6500 #161330

Conversation

ArielCPU commented Sep 30, 2025

Uh oh!

github-actions bot commented Sep 30, 2025

Uh oh!

llvmbot commented Sep 30, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

llvmbot commented Sep 30, 2025

Uh oh!

ArielCPU commented Oct 12, 2025

Uh oh!

yingopq commented Oct 13, 2025

Uh oh!

ArielCPU commented Oct 13, 2025

Uh oh!

yingopq commented Oct 13, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

ArielCPU commented Oct 13, 2025

Uh oh!

Uh oh!

github-actions bot commented Oct 13, 2025

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

llvmbot commented Sep 30, 2025 •

edited

Loading

yingopq commented Oct 13, 2025 •

edited

Loading