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[RISCV] Fix copy/paste mistake in Sh3Add_UWPat. #161923
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This pattern appears to be a copy of the pattern in Sh3AddPat but using sh3add.uw instead of sh3add. I think this is mistake and the pattern should be the equivalent of the first pattern from Sh1Add_UWPat and Sh2Add_UWPat. These classes were created to share with Andes in a788a1a, but there was so many test changes in there that we must have overlooked the changes to Zba codegen.
@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesThis pattern appears to be a copy of the pattern in Sh3AddPat but using sh3add.uw instead of sh3add. I think this is mistake and the pattern should be the equivalent of the first pattern from Sh1Add_UWPat and Sh2Add_UWPat. These classes were created to share with Andes in a788a1a, but there was so many test changes in there that we must have overlooked the changes to Zba codegen. Full diff: https://github.com/llvm/llvm-project/pull/161923.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index ce21d831250b2..8d9b7776ea430 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -808,9 +808,9 @@ multiclass Sh2Add_UWPat<Instruction sh2add_uw> {
}
multiclass Sh3Add_UWPat<Instruction sh3add_uw> {
- def : Pat<(i64 (add_like_non_imm12 (and GPR:$rs1, 0xFFFFFFF8),
+ def : Pat<(i64 (add_like_non_imm12 (and (shl GPR:$rs1, (i64 3)), 0x7FFFFFFFF),
(XLenVT GPR:$rs2))),
- (sh3add_uw (XLenVT (SRLIW GPR:$rs1, 3)), GPR:$rs2)>;
+ (sh3add_uw GPR:$rs1, GPR:$rs2)>;
// Use SRLI to clear the LSBs and SHXADD_UW to mask and shift.
def : Pat<(i64 (add_like_non_imm12 (and GPR:$rs1, 0x7FFFFFFF8),
(XLenVT GPR:$rs2))),
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index c028d25169749..7fd76262d547a 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -409,15 +409,11 @@ define i64 @sh3adduw_2(i64 %0, i64 %1) {
;
; RV64ZBA-LABEL: sh3adduw_2:
; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: slli a0, a0, 3
-; RV64ZBA-NEXT: srli a0, a0, 3
; RV64ZBA-NEXT: sh3add.uw a0, a0, a1
; RV64ZBA-NEXT: ret
;
; RV64XANDESPERF-LABEL: sh3adduw_2:
; RV64XANDESPERF: # %bb.0:
-; RV64XANDESPERF-NEXT: slli a0, a0, 3
-; RV64XANDESPERF-NEXT: srli a0, a0, 3
; RV64XANDESPERF-NEXT: nds.lea.d.ze a0, a1, a0
; RV64XANDESPERF-NEXT: ret
%3 = shl i64 %0, 3
@@ -436,15 +432,11 @@ define i64 @sh3adduw_3(i64 %0, i64 %1) {
;
; RV64ZBA-LABEL: sh3adduw_3:
; RV64ZBA: # %bb.0:
-; RV64ZBA-NEXT: slli a0, a0, 3
-; RV64ZBA-NEXT: srli a0, a0, 3
; RV64ZBA-NEXT: sh3add.uw a0, a0, a1
; RV64ZBA-NEXT: ret
;
; RV64XANDESPERF-LABEL: sh3adduw_3:
; RV64XANDESPERF: # %bb.0:
-; RV64XANDESPERF-NEXT: slli a0, a0, 3
-; RV64XANDESPERF-NEXT: srli a0, a0, 3
; RV64XANDESPERF-NEXT: nds.lea.d.ze a0, a1, a0
; RV64XANDESPERF-NEXT: ret
%3 = shl i64 %0, 3
@@ -2681,7 +2673,7 @@ define i64 @srliw_3_sh3add(ptr %0, i32 signext %1) {
; RV64ZBA-LABEL: srliw_3_sh3add:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: srliw a1, a1, 3
-; RV64ZBA-NEXT: sh3add.uw a0, a1, a0
+; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: ld a0, 0(a0)
; RV64ZBA-NEXT: ret
;
|
; RV64ZBA-LABEL: srliw_3_sh3add: | ||
; RV64ZBA: # %bb.0: | ||
; RV64ZBA-NEXT: srliw a1, a1, 3 | ||
; RV64ZBA-NEXT: sh3add.uw a0, a1, a0 |
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srliw always puts 0s in the upper 32 bits so the .uw here isn't necessary. So I don't think the mistake can cause a miscompile.
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LGTM
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/141/builds/12068 Here is the relevant piece of the build log for the reference
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This pattern appears to be a copy of the pattern in Sh3AddPat but using sh3add.uw instead of sh3add. I think this is a mistake and the pattern should be the equivalent of the first pattern from Sh1Add_UWPat and Sh2Add_UWPat.
These classes were created to share with Andes in a788a1a, but there was so many test changes in there that we must have overlooked the changes to Zba codegen.