Skip to content

Conversation

@jeonghm9764
Copy link

@jeonghm9764 jeonghm9764 commented Nov 15, 2025

module {
  func.func @main(%arg17: memref<1000xf32, strided<[?], offset: ?>>) -> memref<1x1000xf32> {
    %alloc_342 = memref.alloc() {alignment = 64 : i64} : memref<1x1x1000xf32>
    %alloc_343 = memref.alloc() {alignment = 64 : i64} : memref<1x1000xf32>
    affine.for %arg89 = 0 to 1 {
      affine.for %arg90 = 0 to 1000 {
        %0:2 = affine.delinearize_index %arg89 into (1, 1) : index, index
        %1 = affine.load %alloc_342[%0#0, %0#1, %arg90] : memref<1x1x1000xf32>
        %2 = affine.linearize_index disjoint [%arg89, %arg90] by (1, 1000) : index
        %3 = affine.load %arg17[%2] : memref<1000xf32, strided<[?], offset: ?>>
        %4 = arith.addf %1, %3 : f32
        affine.store %4, %alloc_343[%arg89, %arg90] : memref<1x1000xf32>
      }
    }
    return %alloc_343 : memref<1x1000xf32>
  }
}
mlir-opt test.mlir
error: expected ']' in affine map
        %1 = affine.load %alloc_342[%0#0, %0#1, %arg90] : memref<1x1x1000xf32>

It seems that there is a bug in affine.load operation's affine map of SSA ids handling where its values are numbered. (%0#0, %0#1, ...) dimsAndSymbols in AffineParser only takes the name of the value %0, but not #0, and thinks %0 is already parsed when checking redundancy for %0#1. I am not sure if checking for redundancy is necessary here, but removing the check works.

@github-actions
Copy link

Thank you for submitting a Pull Request (PR) to the LLVM Project!

This PR will be automatically labeled and the relevant teams will be notified.

If you wish to, you can add reviewers by using the "Reviewers" section on this page.

If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using @ followed by their GitHub username.

If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers.

If you have further questions, they may be answered by the LLVM GitHub User Guide.

You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums.

@jeonghm9764 jeonghm9764 marked this pull request as ready for review November 15, 2025 05:31
@llvmbot llvmbot added mlir:core MLIR Core Infrastructure mlir labels Nov 15, 2025
@llvmbot
Copy link
Member

llvmbot commented Nov 15, 2025

@llvm/pr-subscribers-mlir-affine

@llvm/pr-subscribers-mlir-core

Author: Paul Jeong (jeonghm9764)

Changes
module {
  func.func @<!-- -->main(%arg17: memref&lt;1000xf32, strided&lt;[?], offset: ?&gt;&gt;) -&gt; memref&lt;1x1000xf32&gt; {
    %alloc_342 = memref.alloc() {alignment = 64 : i64} : memref&lt;1x1x1000xf32&gt;
    %alloc_343 = memref.alloc() {alignment = 64 : i64} : memref&lt;1x1000xf32&gt;
    affine.for %arg89 = 0 to 1 {
      affine.for %arg90 = 0 to 1000 {
        %0:2 = affine.delinearize_index %arg89 into (1, 1) : index, index
        %1 = affine.load %alloc_342[%0#<!-- -->0, %0#<!-- -->1, %arg90] : memref&lt;1x1x1000xf32&gt;
        %2 = affine.linearize_index disjoint [%arg89, %arg90] by (1, 1000) : index
        %3 = affine.load %arg17[%2] : memref&lt;1000xf32, strided&lt;[?], offset: ?&gt;&gt;
        %4 = arith.addf %1, %3 : f32
        affine.store %4, %alloc_343[%arg89, %arg90] : memref&lt;1x1000xf32&gt;
      }
    }
    return %alloc_343 : memref&lt;1x1000xf32&gt;
  }
}


error: expected ']' in affine map
        %1 = affine.load %alloc_342[%0#<!-- -->0, %0#<!-- -->1, %arg90] : memref&lt;1x1x1000xf32&gt;

It seems that there is a bug in affine.load operation's affine map of SSA ids handling where its values are numbered. (%0#0, %0#1, ...) dimsAndSymbols in AffineParser only takes the name of the value %0, but not #0, and thinks %0 is already parsed when checking redundancy for %0#1. I am not sure if checking for redundancy is necessary here, but removing the check works.


Full diff: https://github.com/llvm/llvm-project/pull/168175.diff

1 Files Affected:

  • (modified) mlir/lib/AsmParser/AffineParser.cpp (-7)
diff --git a/mlir/lib/AsmParser/AffineParser.cpp b/mlir/lib/AsmParser/AffineParser.cpp
index 1797611858c06..8f7fa3877aa18 100644
--- a/mlir/lib/AsmParser/AffineParser.cpp
+++ b/mlir/lib/AsmParser/AffineParser.cpp
@@ -311,13 +311,6 @@ AffineExpr AffineParser::parseSSAIdExpr(bool isSymbol) {
   if (getToken().isNot(Token::percent_identifier))
     return emitWrongTokenError("expected ssa identifier"), nullptr;
   auto name = getTokenSpelling();
-  // Check if we already parsed this SSA id.
-  for (auto entry : dimsAndSymbols) {
-    if (entry.first == name) {
-      consumeToken(Token::percent_identifier);
-      return entry.second;
-    }
-  }
   // Parse the SSA id and add an AffineDim/SymbolExpr to represent it.
   if (parseElement(isSymbol))
     return nullptr;

@llvmbot
Copy link
Member

llvmbot commented Nov 15, 2025

@llvm/pr-subscribers-mlir

Author: Paul Jeong (jeonghm9764)

Changes
module {
  func.func @<!-- -->main(%arg17: memref&lt;1000xf32, strided&lt;[?], offset: ?&gt;&gt;) -&gt; memref&lt;1x1000xf32&gt; {
    %alloc_342 = memref.alloc() {alignment = 64 : i64} : memref&lt;1x1x1000xf32&gt;
    %alloc_343 = memref.alloc() {alignment = 64 : i64} : memref&lt;1x1000xf32&gt;
    affine.for %arg89 = 0 to 1 {
      affine.for %arg90 = 0 to 1000 {
        %0:2 = affine.delinearize_index %arg89 into (1, 1) : index, index
        %1 = affine.load %alloc_342[%0#<!-- -->0, %0#<!-- -->1, %arg90] : memref&lt;1x1x1000xf32&gt;
        %2 = affine.linearize_index disjoint [%arg89, %arg90] by (1, 1000) : index
        %3 = affine.load %arg17[%2] : memref&lt;1000xf32, strided&lt;[?], offset: ?&gt;&gt;
        %4 = arith.addf %1, %3 : f32
        affine.store %4, %alloc_343[%arg89, %arg90] : memref&lt;1x1000xf32&gt;
      }
    }
    return %alloc_343 : memref&lt;1x1000xf32&gt;
  }
}


error: expected ']' in affine map
        %1 = affine.load %alloc_342[%0#<!-- -->0, %0#<!-- -->1, %arg90] : memref&lt;1x1x1000xf32&gt;

It seems that there is a bug in affine.load operation's affine map of SSA ids handling where its values are numbered. (%0#0, %0#1, ...) dimsAndSymbols in AffineParser only takes the name of the value %0, but not #0, and thinks %0 is already parsed when checking redundancy for %0#1. I am not sure if checking for redundancy is necessary here, but removing the check works.


Full diff: https://github.com/llvm/llvm-project/pull/168175.diff

1 Files Affected:

  • (modified) mlir/lib/AsmParser/AffineParser.cpp (-7)
diff --git a/mlir/lib/AsmParser/AffineParser.cpp b/mlir/lib/AsmParser/AffineParser.cpp
index 1797611858c06..8f7fa3877aa18 100644
--- a/mlir/lib/AsmParser/AffineParser.cpp
+++ b/mlir/lib/AsmParser/AffineParser.cpp
@@ -311,13 +311,6 @@ AffineExpr AffineParser::parseSSAIdExpr(bool isSymbol) {
   if (getToken().isNot(Token::percent_identifier))
     return emitWrongTokenError("expected ssa identifier"), nullptr;
   auto name = getTokenSpelling();
-  // Check if we already parsed this SSA id.
-  for (auto entry : dimsAndSymbols) {
-    if (entry.first == name) {
-      consumeToken(Token::percent_identifier);
-      return entry.second;
-    }
-  }
   // Parse the SSA id and add an AffineDim/SymbolExpr to represent it.
   if (parseElement(isSymbol))
     return nullptr;

Copy link
Collaborator

@joker-eph joker-eph left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

We need a test for this, can you add one?

I'm also not sure this is the right fix, it does not build the same expression, but maybe some CSE is already done on the AffineExpr later anyway?

@jeonghm9764
Copy link
Author

jeonghm9764 commented Nov 18, 2025

Added a test.

I think affine.load should be handled differently compared to normal affine maps. For example, for normal affine maps, redundant dimension can be optimized away, and I think that is what the removed lines are checking for. However, for affine.load, same value can appear multiple times (like in case where you want to access diagonal elements: array[i, i])

I am not an expert on MLIR so I might be wrong. However, I think not being able to parse something that is legal and generated by mlir-opt is still a bug. Hope this can be fixed later if mine is not the right fix.

@joker-eph
Copy link
Collaborator

Adding @bondhugula and @ftynse to chime in.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

mlir:affine mlir:core MLIR Core Infrastructure mlir

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants