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[clang][MIPS] Add support for mipsel-windows-* targets #107744

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[clang][MIPS] Add support for mipsel-windows-* targets #107744

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193f3d3
[Triple] Make mipsel-*-windows-* use COFF files by default
hpoussin Oct 22, 2023
f99b2ea
[COFF] Add MIPS relocation types
hpoussin Oct 22, 2023
db61c91
[yaml2obj][objdump] Handle IMAGE_FILE_MACHINE_R4000 machine type and …
hpoussin Oct 22, 2023
38bcda6
[MC][Mips] Rename MipsMCAsmInfo to MipsELFMCAsmInfo
hpoussin Oct 22, 2023
b02203d
[MC][Mips] Add MipsWinCOFFObjectWriter/MipsWinCOFFStreamer
hpoussin Oct 22, 2023
95a56b6
[MC][Mips] Add the required IMAGE_REL_MIPS_PAIR relocation after IMAG…
hpoussin Oct 22, 2023
40f4c9a
[MC][CodeGen][Mips] Add CodeView mapping
hpoussin Oct 22, 2023
d6ce440
[Mips] Handle declspec(dllimport) on mipsel-windows-* triples
hpoussin Oct 22, 2023
965c46d
[llvm-lib] Handle MIPS architecture
hpoussin Oct 22, 2023
607f719
[llvm-dlltool] Handle MIPS architecture
hpoussin Oct 22, 2023
e6157bb
[Clang][MIPS] Create specific targets for MIPS PE/COFF
hpoussin Oct 22, 2023
fda9245
[Clang][MIPS] Create correct linker arguments for Windows toolchains
hpoussin Nov 10, 2023
9deeff4
[Clang][MIPS] Send correct architecture for MinGW toolchains
hpoussin Nov 10, 2023
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1 change: 1 addition & 0 deletions lld/COFF/Config.h
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Expand Up @@ -40,6 +40,7 @@ static const auto ARM64EC = llvm::COFF::IMAGE_FILE_MACHINE_ARM64EC;
static const auto ARM64X = llvm::COFF::IMAGE_FILE_MACHINE_ARM64X;
static const auto ARMNT = llvm::COFF::IMAGE_FILE_MACHINE_ARMNT;
static const auto I386 = llvm::COFF::IMAGE_FILE_MACHINE_I386;
static const auto MIPS = llvm::COFF::IMAGE_FILE_MACHINE_R4000;
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@mstorsjo mstorsjo Sep 9, 2024

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This part (adding a yet-unused shorthand in lld/COFF/Config.h) of this commit (primarily llvm/lib/Object stuff) seems unrelated and should be moved to a later commit.


enum class ExportSource {
Unset,
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18 changes: 18 additions & 0 deletions llvm/include/llvm/BinaryFormat/COFF.h
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Expand Up @@ -417,6 +417,24 @@ enum RelocationTypesARM64 : unsigned {
IMAGE_REL_ARM64_REL32 = 0x0011,
};

enum RelocationTypesMips : unsigned {
IMAGE_REL_MIPS_ABSOLUTE = 0x0000,
IMAGE_REL_MIPS_REFHALF = 0x0001,
IMAGE_REL_MIPS_REFWORD = 0x0002,
IMAGE_REL_MIPS_JMPADDR = 0x0003,
IMAGE_REL_MIPS_REFHI = 0x0004,
IMAGE_REL_MIPS_REFLO = 0x0005,
IMAGE_REL_MIPS_GPREL = 0x0006,
IMAGE_REL_MIPS_LITERAL = 0x0007,
IMAGE_REL_MIPS_SECTION = 0x000A,
IMAGE_REL_MIPS_SECREL = 0x000B,
IMAGE_REL_MIPS_SECRELLO = 0x000C,
IMAGE_REL_MIPS_SECRELHI = 0x000D,
IMAGE_REL_MIPS_JMPADDR16 = 0x0010,
IMAGE_REL_MIPS_REFWORDNB = 0x0022,
IMAGE_REL_MIPS_PAIR = 0x0025,
};

enum DynamicRelocationType : unsigned {
IMAGE_DYNAMIC_RELOCATION_GUARD_RF_PROLOGUE = 1,
IMAGE_DYNAMIC_RELOCATION_GUARD_RF_EPILOGUE = 2,
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88 changes: 87 additions & 1 deletion llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
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Expand Up @@ -16,7 +16,8 @@

#if !defined(CV_REGISTERS_ALL) && !defined(CV_REGISTERS_X86) && \
!defined(CV_REGISTERS_ARM) && \
!defined(CV_REGISTERS_ARM64)
!defined(CV_REGISTERS_ARM64) && \
!defined(CV_REGISTERS_MIPS)
#error Need include at least one register set.
#endif

Expand Down Expand Up @@ -793,3 +794,88 @@ CV_REGISTER(ARM64_H31, 301)
#pragma pop_macro("ARM64_FPCR")

#endif // defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_ARM64)

#if defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_MIPS)

// MIPS registers
CV_REGISTER(MIPS_NOREG, 0)

// General purpose integer registers

CV_REGISTER(MIPS_ZERO, 10)
CV_REGISTER(MIPS_AT, 11)
CV_REGISTER(MIPS_V0, 12)
CV_REGISTER(MIPS_V1, 13)
CV_REGISTER(MIPS_A0, 14)
CV_REGISTER(MIPS_A1, 15)
CV_REGISTER(MIPS_A2, 16)
CV_REGISTER(MIPS_A3, 17)
CV_REGISTER(MIPS_T0, 18)
CV_REGISTER(MIPS_T1, 19)
CV_REGISTER(MIPS_T2, 20)
CV_REGISTER(MIPS_T3, 21)
CV_REGISTER(MIPS_T4, 22)
CV_REGISTER(MIPS_T5, 23)
CV_REGISTER(MIPS_T6, 24)
CV_REGISTER(MIPS_T7, 25)
CV_REGISTER(MIPS_S0, 26)
CV_REGISTER(MIPS_S1, 27)
CV_REGISTER(MIPS_S2, 28)
CV_REGISTER(MIPS_S3, 29)
CV_REGISTER(MIPS_S4, 30)
CV_REGISTER(MIPS_S5, 31)
CV_REGISTER(MIPS_S6, 32)
CV_REGISTER(MIPS_S7, 33)
CV_REGISTER(MIPS_T8, 34)
CV_REGISTER(MIPS_T9, 35)
CV_REGISTER(MIPS_K0, 36)
CV_REGISTER(MIPS_K1, 37)
CV_REGISTER(MIPS_GP, 38)
CV_REGISTER(MIPS_SP, 39)
CV_REGISTER(MIPS_S8, 40)
CV_REGISTER(MIPS_RA, 41)
CV_REGISTER(MIPS_LO, 42)
CV_REGISTER(MIPS_HI, 43)

// Status registers

CV_REGISTER(MIPS_Fir, 50)
CV_REGISTER(MIPS_Psr, 51)

// Floating-point registers

CV_REGISTER(MIPS_F0, 60)
CV_REGISTER(MIPS_F1, 61)
CV_REGISTER(MIPS_F2, 62)
CV_REGISTER(MIPS_F3, 63)
CV_REGISTER(MIPS_F4, 64)
CV_REGISTER(MIPS_F5, 65)
CV_REGISTER(MIPS_F6, 66)
CV_REGISTER(MIPS_F7, 67)
CV_REGISTER(MIPS_F8, 68)
CV_REGISTER(MIPS_F9, 69)
CV_REGISTER(MIPS_F10, 70)
CV_REGISTER(MIPS_F11, 71)
CV_REGISTER(MIPS_F12, 72)
CV_REGISTER(MIPS_F13, 73)
CV_REGISTER(MIPS_F14, 74)
CV_REGISTER(MIPS_F15, 75)
CV_REGISTER(MIPS_F16, 76)
CV_REGISTER(MIPS_F17, 77)
CV_REGISTER(MIPS_F18, 78)
CV_REGISTER(MIPS_F19, 79)
CV_REGISTER(MIPS_F20, 80)
CV_REGISTER(MIPS_F21, 81)
CV_REGISTER(MIPS_F22, 82)
CV_REGISTER(MIPS_F23, 83)
CV_REGISTER(MIPS_F24, 84)
CV_REGISTER(MIPS_F25, 85)
CV_REGISTER(MIPS_F26, 86)
CV_REGISTER(MIPS_F27, 87)
CV_REGISTER(MIPS_F28, 88)
CV_REGISTER(MIPS_F29, 89)
CV_REGISTER(MIPS_F30, 90)
CV_REGISTER(MIPS_F31, 91)
CV_REGISTER(MIPS_Fsr, 92)

#endif // defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_MIPS)
2 changes: 2 additions & 0 deletions llvm/include/llvm/Object/WindowsMachineFlag.h
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Expand Up @@ -43,6 +43,8 @@ template <typename T> Triple::ArchType getMachineArchType(T machine) {
case COFF::IMAGE_FILE_MACHINE_ARM64EC:
case COFF::IMAGE_FILE_MACHINE_ARM64X:
return llvm::Triple::ArchType::aarch64;
case COFF::IMAGE_FILE_MACHINE_R4000:
return llvm::Triple::ArchType::mipsel;
default:
return llvm::Triple::ArchType::UnknownArch;
}
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5 changes: 5 additions & 0 deletions llvm/include/llvm/ObjectYAML/COFFYAML.h
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Expand Up @@ -179,6 +179,11 @@ struct ScalarEnumerationTraits<COFF::RelocationTypeAMD64> {
static void enumeration(IO &IO, COFF::RelocationTypeAMD64 &Value);
};

template <>
struct ScalarEnumerationTraits<COFF::RelocationTypesMips> {
static void enumeration(IO &IO, COFF::RelocationTypesMips &Value);
};

template <>
struct ScalarEnumerationTraits<COFF::RelocationTypesARM> {
static void enumeration(IO &IO, COFF::RelocationTypesARM &Value);
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2 changes: 2 additions & 0 deletions llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
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Expand Up @@ -125,6 +125,8 @@ static CPUType mapArchToCVCPUType(Triple::ArchType Type) {
return CPUType::ARMNT;
case Triple::ArchType::aarch64:
return CPUType::ARM64;
case Triple::ArchType::mipsel:
return CPUType::MIPS;
default:
report_fatal_error("target architecture doesn't map to a CodeView CPUType");
}
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17 changes: 15 additions & 2 deletions llvm/lib/MC/WinCOFFObjectWriter.cpp
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Expand Up @@ -773,7 +773,10 @@ void WinCOFFWriter::assignFileOffsets(MCAssembler &Asm) {

for (auto &Relocation : Sec->Relocations) {
assert(Relocation.Symb->getIndex() != -1);
Relocation.Data.SymbolTableIndex = Relocation.Symb->getIndex();
if (Header.Machine != COFF::IMAGE_FILE_MACHINE_R4000 ||
Relocation.Data.Type != COFF::IMAGE_REL_MIPS_PAIR) {
Relocation.Data.SymbolTableIndex = Relocation.Symb->getIndex();
}
}
}

Expand Down Expand Up @@ -967,8 +970,18 @@ void WinCOFFWriter::recordRelocation(MCAssembler &Asm,
if (Fixup.getKind() == FK_SecRel_2)
FixedValue = 0;

if (OWriter.TargetObjectWriter->recordRelocation(Fixup))
if (OWriter.TargetObjectWriter->recordRelocation(Fixup)) {
Sec->Relocations.push_back(Reloc);
if (Header.Machine == COFF::IMAGE_FILE_MACHINE_R4000 &&
(Reloc.Data.Type == COFF::IMAGE_REL_MIPS_REFHI ||
Reloc.Data.Type == COFF::IMAGE_REL_MIPS_SECRELHI)) {
// IMAGE_REL_MIPS_REFHI and IMAGE_REL_MIPS_SECRELHI *must*
// be followed by IMAGE_REL_MIPS_PAIR
auto RelocPair = Reloc;
RelocPair.Data.Type = COFF::IMAGE_REL_MIPS_PAIR;
Sec->Relocations.push_back(RelocPair);
}
}
}

static std::time_t getTime() {
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26 changes: 26 additions & 0 deletions llvm/lib/Object/COFFObjectFile.cpp
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Expand Up @@ -1132,6 +1132,8 @@ StringRef COFFObjectFile::getFileFormatName() const {
return "COFF-ARM64EC";
case COFF::IMAGE_FILE_MACHINE_ARM64X:
return "COFF-ARM64X";
case COFF::IMAGE_FILE_MACHINE_R4000:
return "COFF-R4000";
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@mstorsjo mstorsjo Sep 9, 2024

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Hmm, do we want to label this as COFF-R4000, or would just COFF-MIPS be more easily accessible?

I see that there are a couple other IMAGE_FILE_MACHINE_* constants for MIPS variants - how relevant are they?

If the R4000 is the only one that actually is being used, I'd almost go with labelling this just COFF-MIPS.

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@FlyGoat FlyGoat Oct 14, 2024

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I asked Microsoft for clarification but no response so far: MicrosoftDocs/win32#1846

default:
return "COFF-<unknown arch>";
}
Expand Down Expand Up @@ -1465,6 +1467,27 @@ StringRef COFFObjectFile::getRelocationTypeName(uint16_t Type) const {
return "Unknown";
}
break;
case Triple::mipsel:
switch (Type) {
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_ABSOLUTE);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_REFHALF);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_REFWORD);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_JMPADDR);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_REFHI);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_REFLO);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_GPREL);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_LITERAL);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_SECTION);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_SECREL);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_SECRELLO);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_SECRELHI);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_JMPADDR16);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_REFWORDNB);
LLVM_COFF_SWITCH_RELOC_TYPE_NAME(IMAGE_REL_MIPS_PAIR);
default:
return "Unknown";
}
break;
default:
return "Unknown";
}
Expand Down Expand Up @@ -2326,6 +2349,9 @@ ResourceSectionRef::getContents(const coff_resource_data_entry &Entry) {
case Triple::aarch64:
RVAReloc = COFF::IMAGE_REL_ARM64_ADDR32NB;
break;
case Triple::mipsel:
RVAReloc = COFF::IMAGE_REL_MIPS_REFWORDNB;
break;
default:
return createStringError(object_error::parse_failed,
"unsupported architecture");
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4 changes: 4 additions & 0 deletions llvm/lib/Object/WindowsMachineFlag.cpp
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Expand Up @@ -28,6 +28,8 @@ COFF::MachineTypes llvm::getMachineType(StringRef S) {
.Case("arm64", COFF::IMAGE_FILE_MACHINE_ARM64)
.Case("arm64ec", COFF::IMAGE_FILE_MACHINE_ARM64EC)
.Case("arm64x", COFF::IMAGE_FILE_MACHINE_ARM64X)
.Case("mips", COFF::IMAGE_FILE_MACHINE_R4000) // also handle mips (big-endian) because we want to support '/machine:MIPS'
.Case("mipsel", COFF::IMAGE_FILE_MACHINE_R4000)
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@mstorsjo mstorsjo Sep 9, 2024

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I don't think we should accept mipsel here, and the comment about big-endian above feels confusing/misleading.

This switch is only for mapping arch names from the MS tool /machine: flags, to the corresponding COFF::IMAGE_FILE_MACHINE_* values. I presume that no MS tool ever accepted /machine:mipsel right? Then we don't need that value here. And as all Windows/COFF MIPS was little-endian (I presume) we don't need claim anything to be big endian.

It's just that arch names in different namespaces can mean different things. In MS tools, /machine:mips unambiguously means little endian mips, while the corresponding thing in a triple is mipsel-*.

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@FlyGoat FlyGoat Oct 14, 2024

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FYI /machine: for MIPS is MIPS, MIPS16, MIPSFPU, MIPSFPU16, MIPSR41XX. I think our scope is limited to MIPS so far.

.Default(COFF::IMAGE_FILE_MACHINE_UNKNOWN);
}

Expand All @@ -45,6 +47,8 @@ StringRef llvm::machineToStr(COFF::MachineTypes MT) {
return "x64";
case COFF::IMAGE_FILE_MACHINE_I386:
return "x86";
case COFF::IMAGE_FILE_MACHINE_R4000:
return "mipsel";
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@mstorsjo mstorsjo Sep 9, 2024

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This seems wrong - this should return the canonical name for the /machine: flag for this machine type, which I presume is mips.

default:
llvm_unreachable("unknown machine type");
}
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3 changes: 3 additions & 0 deletions llvm/lib/Object/WindowsResource.cpp
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Expand Up @@ -992,6 +992,9 @@ void WindowsResourceCOFFWriter::writeFirstSectionRelocations() {
case Triple::aarch64:
Reloc->Type = COFF::IMAGE_REL_ARM64_ADDR32NB;
break;
case Triple::mipsel:
Reloc->Type = COFF::IMAGE_REL_MIPS_REFWORDNB;
break;
default:
llvm_unreachable("unknown machine type");
}
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23 changes: 23 additions & 0 deletions llvm/lib/ObjectYAML/COFFYAML.cpp
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Expand Up @@ -183,6 +183,25 @@ void ScalarEnumerationTraits<COFF::RelocationTypeAMD64>::enumeration(
ECase(IMAGE_REL_AMD64_SSPAN32);
}

void ScalarEnumerationTraits<COFF::RelocationTypesMips>::enumeration(
IO &IO, COFF::RelocationTypesMips &Value) {
ECase(IMAGE_REL_MIPS_ABSOLUTE);
ECase(IMAGE_REL_MIPS_REFHALF);
ECase(IMAGE_REL_MIPS_REFWORD);
ECase(IMAGE_REL_MIPS_JMPADDR);
ECase(IMAGE_REL_MIPS_REFHI);
ECase(IMAGE_REL_MIPS_REFLO);
ECase(IMAGE_REL_MIPS_GPREL);
ECase(IMAGE_REL_MIPS_LITERAL);
ECase(IMAGE_REL_MIPS_SECTION);
ECase(IMAGE_REL_MIPS_SECREL);
ECase(IMAGE_REL_MIPS_SECRELLO);
ECase(IMAGE_REL_MIPS_SECRELHI);
ECase(IMAGE_REL_MIPS_JMPADDR16);
ECase(IMAGE_REL_MIPS_REFWORDNB);
ECase(IMAGE_REL_MIPS_PAIR);
}

void ScalarEnumerationTraits<COFF::RelocationTypesARM>::enumeration(
IO &IO, COFF::RelocationTypesARM &Value) {
ECase(IMAGE_REL_ARM_ABSOLUTE);
Expand Down Expand Up @@ -427,6 +446,10 @@ void MappingTraits<COFFYAML::Relocation>::mapping(IO &IO,
MappingNormalization<NType<COFF::RelocationTypeAMD64>, uint16_t> NT(
IO, Rel.Type);
IO.mapRequired("Type", NT->Type);
} else if (H.Machine == COFF::IMAGE_FILE_MACHINE_R4000) {
MappingNormalization<NType<COFF::RelocationTypesMips>, uint16_t> NT(
IO, Rel.Type);
IO.mapRequired("Type", NT->Type);
} else if (H.Machine == COFF::IMAGE_FILE_MACHINE_ARMNT) {
MappingNormalization<NType<COFF::RelocationTypesARM>, uint16_t> NT(
IO, Rel.Type);
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp
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Expand Up @@ -171,6 +171,9 @@ void ScalarEnumerationTraits<RegisterId>::enumeration(IO &io, RegisterId &Reg) {
case COFF::IMAGE_FILE_MACHINE_ARM64X:
CpuType = CPUType::ARM64;
break;
case COFF::IMAGE_FILE_MACHINE_R4000:
CpuType = CPUType::MIPSIII;
break;
}

if (CpuType)
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
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Expand Up @@ -12,6 +12,8 @@ add_llvm_component_library(LLVMMipsDesc
MipsNaClELFStreamer.cpp
MipsOptionRecord.cpp
MipsTargetStreamer.cpp
MipsWinCOFFObjectWriter.cpp
MipsWinCOFFStreamer.cpp

LINK_COMPONENTS
CodeGenTypes
Expand Down
21 changes: 21 additions & 0 deletions llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
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Expand Up @@ -597,10 +597,31 @@ bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const {
return false;
}

namespace {

class WindowsMipsAsmBackend : public MipsAsmBackend {
public:
WindowsMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI)
: MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), false) {
}

std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const override {
return createMipsWinCOFFObjectWriter();
}
};

} // end anonymous namespace

MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple();
if (TheTriple.isOSWindows())
return new WindowsMipsAsmBackend(T, MRI, STI);

MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(),
STI.getCPU(), Options);
return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
Expand Down
28 changes: 25 additions & 3 deletions llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
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Expand Up @@ -16,10 +16,10 @@

using namespace llvm;

void MipsMCAsmInfo::anchor() { }
void MipsELFMCAsmInfo::anchor() { }

MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple,
const MCTargetOptions &Options) {
MipsELFMCAsmInfo::MipsELFMCAsmInfo(const Triple &TheTriple,
const MCTargetOptions &Options) {
IsLittleEndian = TheTriple.isLittleEndian();

MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TheTriple, "", Options);
Expand Down Expand Up @@ -51,3 +51,25 @@ MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple,
DwarfRegNumForCFI = true;
HasMipsExpressions = true;
}

void MipsCOFFMCAsmInfoMicrosoft::anchor() { }

MipsCOFFMCAsmInfoMicrosoft::MipsCOFFMCAsmInfoMicrosoft() {
WinEHEncodingType = WinEH::EncodingType::Itanium;
CommentString = ";";
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@mstorsjo mstorsjo Sep 9, 2024

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In general, I would recommend against using ; as comment string here.

While this is the asm dialect for Microsoft variants, this still is within the scope of GNU assembler style, produced and consumed by clang and llvm-mc and similar tools.

For the full standalone Microsoft style assembly, on x86 we have the separate llvm-ml tool. And on aarch64, we've changed CommentString to use // for the microsoft variant, just like for the GNU/ELF variants, in order to be able to build e.g. compiler-rt assembly sources for the microsoft variants too - see 71c29b4.


ExceptionsType = ExceptionHandling::WinEH;

AllowAtInName = true;
}

void MipsCOFFMCAsmInfoGNU::anchor() { }

MipsCOFFMCAsmInfoGNU::MipsCOFFMCAsmInfoGNU() {
HasSingleParameterDotFile = true;
WinEHEncodingType = WinEH::EncodingType::Itanium;

ExceptionsType = ExceptionHandling::WinEH;

AllowAtInName = true;
}
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